Added module->uniquify()

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 95b3c407e244eb2fc95443fc4608f93f9c894777..0440f88e59703d0403d99faf6232b7fd22cb531a 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -603,9 +603,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 
                // log("  importing net %s.\n", net->Name());
 
-               std::string wire_name = RTLIL::escape_id(net->Name());
-               while (module->count_id(wire_name))
-                       wire_name += "_";
+               RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(net->Name()));
                RTLIL::Wire *wire = module->addWire(wire_name);
                import_attributes(wire->attributes, net);
 
@@ -627,9 +625,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
                {
                        // log("  importing netbus %s.\n", netbus->Name());
 
-                       std::string wire_name = RTLIL::escape_id(netbus->Name());
-                       while (module->count_id(wire_name))
-                               wire_name += "_";
+                       RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
                        RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
                        wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
                        import_attributes(wire->attributes, netbus);

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 3df7d83c4489befa14aaec76e2a0034bc750a3c7..60c514d19e64a322fe84fe609cc636b8283a985f 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1108,6 +1108,28 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
        cells_[c2->name] = c2;
 }
 
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
+{
+       int index = 0;
+       return uniquify(name, index);
+}
+
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
+{
+       if (index == 0) {
+               if (count_id(name) == 0)
+                       return name;
+               index++;
+       }
+
+       while (1) {
+               RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
+               if (count_id(new_name) == 0)
+                       return new_name;
+               index++;
+       }
+}
+
 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 {
        if (a->port_id && !b->port_id)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 43e36cbde3b1ed2fa25a1c26d3ada13a53d1ddf1..7e052b091500f7947d5a99579579b579f55d599c 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -625,6 +625,9 @@ public:
        void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
        void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
 
+       RTLIL::IdString uniquify(RTLIL::IdString name);
+       RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
+
        RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
        RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
 

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index a3daf239878471d265f2f1bbc2d0c1dc89b7f37c..cef0a272eb866c0defc2e7e4c3d93bc9aa3bf03c 100644 (file)
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -46,10 +46,7 @@ struct SplitnetsWorker
                if (format.size() > 1)
                        new_wire_name += format.substr(1, 1);
 
-               while (module->count_id(new_wire_name) > 0)
-                       new_wire_name += "_";
-
-               RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
+               RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
                new_wire->port_id = wire->port_id;
                new_wire->port_input = wire->port_input;
                new_wire->port_output = wire->port_output;

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 60580eb4689acdfe0fb9ebeede140d20d5849b60..ab6d5671dd7aac1fe924376a5ad63462fa361230 100644 (file)
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
        // create state register
 
-       std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
-       while (module->count_id(state_wire_name) > 0)
-               state_wire_name += "_";
-
-       RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
+       RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
        RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
        RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");