Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs...

Signed-off-by: Claire Wolf <claire@symbioticeda.com>

diff --cc frontends/ast/simplify.cc
index 5a97079768fb990ee23b4e1cee8739712c08bd60,94ba95e5bf2e4445a0aca0fb61922a2fccda93cf..6ab369817c701e5364513d8e718c533683afbf1e
--- 1/frontends/ast/simplify.cc
--- 2/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@@ -4410,6 -4354,27 +4384,35 @@@ AstNode *AstNode::eval_const_function(A
                stmt->dumpAst(NULL, "stmt> ");
  #endif
  
 -                      if (stmt->is_input && argidx < fcall->children.size())
 -                              variables[stmt->str].val = fcall->children.at(argidx++)->bitsAsConst(variables[stmt->str].val.bits.size());
+               if (stmt->type == AST_WIRE)
+               {
+                       while (stmt->simplify(true, false, false, 1, -1, false, true)) { }
+                       if (!stmt->range_valid)
+                               log_file_error(stmt->filename, stmt->location.first_line, "Can't determine size of variable %s\n%s:%d.%d-%d.%d: ... called from here.\n",
+                                               stmt->str.c_str(), fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column);
+                       variables[stmt->str].val = RTLIL::Const(RTLIL::State::Sx, abs(stmt->range_left - stmt->range_right)+1);
+                       variables[stmt->str].offset = min(stmt->range_left, stmt->range_right);
+                       variables[stmt->str].is_signed = stmt->is_signed;
++                      if (stmt->is_input && argidx < fcall->children.size()) {
++                              int width = variables[stmt->str].val.bits.size();
++                              auto* arg_node = fcall->children.at(argidx++);
++                              if (arg_node->type == AST_CONSTANT) {
++                                      variables[stmt->str].val = arg_node->bitsAsConst(width);
++                              } else {
++                                      log_assert(arg_node->type == AST_REALVALUE);
++                                      variables[stmt->str].val = arg_node->realAsConst(width);
++                              }
++                      }
+                       if (!backup_scope.count(stmt->str))
+                               backup_scope[stmt->str] = current_scope[stmt->str];
+                       current_scope[stmt->str] = stmt;
+ 
+                       block->children.erase(block->children.begin());
+                       continue;
+               }
+ 
+               log_assert(variables.count(str) != 0);
+ 
                if (stmt->type == AST_ASSIGN_EQ)
                {
                        if (stmt->children.at(0)->type == AST_IDENTIFIER && stmt->children.at(0)->children.size() != 0 &&