- Logic analyser with LiteScopeLA:
- Various triggering modules: Term, Range, Edge (add yours! :)
- Run Length Encoder to "compress" data and increase recording depth
+ - Subsampling
+ - Storage qualifier
- Data storage in block rams
[> Possibles improvements
self.data_sink = data_sink = Sink(data_layout(dw))
self.trigger = Signal()
+ self.qualifier = Signal()
self.length = Signal(bits_for(depth))
self.offset = Signal(bits_for(depth))
self.done = Signal()
If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
)
fsm.act("POST_HIT_RECORDING",
- fifo.sink.stb.eq(data_sink.stb),
+ If(self.qualifier,
+ fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
+ ).Else(
+ fifo.sink.stb.eq(data_sink.stb)
+ ),
fifo.sink.data.eq(data_sink.data),
data_sink.ack.eq(fifo.sink.ack),
LiteScopeRecorderUnit.__init__(self, dw, depth)
self._trigger = CSR()
+ self._qualifier = CSRStorage()
self._length = CSRStorage(bits_for(depth))
self._offset = CSRStorage(bits_for(depth))
self._done = CSRStatus()
self.comb += [
self.trigger.eq(self._trigger.re),
+ self.qualifier.eq(self._qualifier.storage),
self.length.eq(self._length.storage),
self.offset.eq(self._offset.storage),
self._done.status.eq(self.done),
Record.connect(rle.source, self.recorder.data_sink)
]
else:
- self.comb += Record.connect(sink, self.recorder.data_sink)
+ self.submodules.delay_buffer = Buffer(self.sink.description)
+ self.comb += [
+ Record.connect(sink, self.delay_buffer.d),
+ Record.connect(self.delay_buffer.q, self.recorder.data_sink)
+ ]
def export(self, vns, filename):
def format_line(*args):
def configure_subsampler(self, n):
self.subsampler_value.write(n-1)
+ def configure_qualifier(self, v):
+ self.recorder_qualifier.write(v)
+
def configure_rle(self, v):
self.rle_enable.write(v)
cond = {"cnt0" : 128} # trigger on cnt0 = 128
la.configure_term(port=0, cond=cond)
la.configure_sum("term")
-la.configure_subsampler(16)
+la.configure_subsampler(1)
+la.configure_qualifier(1)
la.run(offset=128, length=256)
while not la.done():