+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.15 Binary Coded Decimal (BCD) Assist Instructions. Page 111 -->
-
-<!-- The Binary Coded Decimal Assist instructions operate on Binary Coded Decimal -->
-<!-- operands (cbcdtd and addg6s) and Decimal Floating-Point operands (cdtbcd) -->
-<!-- See Chapter 5. for additional information. -->
-
-
-# Convert Declets To Binary Coded Decimal
-
-X-Form
-
-* cdtbcd RA, RS
-
-Pseudo-code:
-
- do i = 0 to 1
- n <- i * 32
- RA[n+0:n+7] <- 0
- RA[n+8:n+19 ] <- DPD_TO_BCD ( (RS)[n+12:n+21] )
- RA[n+20:n+31] <- DPD_TO_BCD ( (RS)[n+22:n+31] )
-
-Special Registers Altered:
-
- None
-
-# Add and Generate Sixes
-
-XO-Form
-
-* addg6s RT,RA,RB
-
-Pseudo-code:
-
- do i = 0 to 15
- dci <- carry_out(RA[4*i:63] + RB[4*i:63])
- c <- ([dc[0]]*4 || [dc[1]]*4 || [dc[2]]*4 || [dc[3]]*4 ||
- [dc[4]]*4 || [dc[5]]*4 || [dc[6]]*4 || [dc[7]]*4 ||
- [dc[8]]*4 || [dc[9]]*4 || [dc[10]]*4 || [dc[11]]*4 ||
- [dc[12]]*4 || [dc[13]]*4 || [dc[14]]*4 || [dc[15]]*4)
- RT <- (¬c) & 0x6666_6666_6666_6666
-
-Special Registers Altered:
-
- None
-
-# Convert Binary Coded Decimal To Declets
-
-X-Form
-
-* cbcdtd RA, RS
-
-Pseudo-code:
-
- do i = 0 to 1
- n <- i * 32
- RA[n+0:n+11] <- 0
- RA[n+12:n+21] <- BCD_TO_DPD ( (RS)[n+8:n+19] )
- RA[n+22:n+31] <- BCD_TO_DPD ( (RS)[n+20:n+31] )
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 2.4 Branch Instructions. Pages 33 - 39 -->
-
-<!-- The sequence of instruction execution can be changed by the Branch -->
-<!-- instructions. Because all instructions are on word boundaries, bits 62 and 63 -->
-<!-- of the generated branch target address are ignored by the processor in -->
-<!-- performing the branch. -->
-
-<!-- target_addr specifies the branch target address. -->
-
-<!-- If AA=0 then the branch target address is the sum of LI || 0b00 sign-extended -->
-<!-- and the address of this instruction, with the high-order 32 bits of the branch -->
-<!-- target address set to 0 in 32-bit mode. -->
-
-<!-- If AA=1 then the branch target address is the value LI || 0b00 sign-extended, -->
-<!-- with the high-order 32 bits of the branch target address set to 0 in 32-bit -->
-<!-- mode. -->
-
-<!-- If LK=1 then the effective address of the instruction following the Branch -->
-<!-- instruction is placed into the Link Register. -->
-
-# Branch
-
-I-Form
-
-* b target_addr (AA=0 LK=0)
-* ba target_addr (AA=1 LK=0)
-* bl target_addr (AA=0 LK=1)
-* bla target_addr (AA=1 LK=1)
-
-Pseudo-code:
-
- if AA then NIA <-iea EXTS(LI || 0b00)
- else NIA <-iea CIA + EXTS(LI || 0b00)
- if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
- LR (if LK=1)
-
-# Branch Conditional
-
-B-Form
-
-* bc BO,BI,target_addr (AA=0 LK=0)
-* bca BO,BI,target_addr (AA=1 LK=0)
-* bcl BO,BI,target_addr (AA=0 LK=1)
-* bcla BO,BI,target_addr (AA=1 LK=1)
-
-Pseudo-code:
-
- if (mode_is_64bit) then M <- 0
- else M <- 32
- if ¬BO[2] then CTR <- CTR - 1
- ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
- cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
- if ctr_ok & cond_ok then
- if AA then NIA <-iea EXTS(BD || 0b00)
- else NIA <-iea CIA + EXTS(BD || 0b00)
- if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
- CTR (if BO2=0)
- LR (if LK=1)
-
-# Branch Conditional to Link Register
-
-XL-Form
-
-* bclr BO,BI,BH (LK=0)
-* bclrl BO,BI,BH (LK=1)
-
-Pseudo-code:
-
- if (mode_is_64bit) then M <- 0
- else M <- 32
- if ¬BO[2] then CTR <- CTR - 1
- ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
- cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
- if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
- if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
- CTR (if BO2=0)
- LR (if LK=1)
-
-# Branch Conditional to Count Register
-
-XL-Form
-
-* bcctr BO,BI,BH (LK=0)
-* bcctrl BO,BI,BH (LK=1)
-
-Pseudo-code:
-
- cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
- if cond_ok then NIA <-iea CTR[0:61] || 0b00
- if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
- LR (if LK=1)
-
-# Branch Conditional to Branch Target Address Register
-
-XL-Form
-
-* bctar BO,BI,BH (LK=0)
-* bctarl BO,BI,BH (LK=1)
-
-Pseudo-code:
-
- if (mode_is_64bit) then M <- 0
- else M <- 32
- if ¬BO[2] then CTR <- CTR - 1
- ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
- cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
- if ctr_ok & cond_ok then NIA <-iea TAR[0:61] || 0b00
- if LK then LR <-iea CIA + 4
-
-Special Registers Altered:
-
- CTR (if BO2=0)
- LR (if LK=1)
-
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.10 Fixed-Point Compare Instructions Pages 84 - 88 -->
-
-<!-- The fixed-point Compare instructions compare the contents of register RA with -->
-<!-- (1) the sign-extended value of the SI field, (2) the zero-extended value of the -->
-<!-- UI field, or (3) the contents of register RB. The comparison is signed for cmpi -->
-<!-- and cmp, and unsigned for cmpli and cmpl. -->
-
-# Compare Immediate
-
-D-Form
-
-* cmpi BF,L,RA,SI
-
-Pseudo-code:
-
- if L = 0 then a <- EXTS((RA)[32:63])
- else a <- (RA)
- if a < EXTS(SI) then c <- 0b100
- else if a > EXTS(SI) then c <- 0b010
- else c <- 0b001
- CR[4*BF+32:4*BF+35] <- c || XER[SO]
-
-Special Registers Altered:
-
- CR field BF
-
-# Compare
-
-X-Form
-
-* cmp BF,L,RA,RB
-
-Pseudo-code:
-
- if L = 0 then
- a <- EXTS((RA)[32:63])
- b <- EXTS((RB)[32:63])
- else
- a <- (RA)
- b <- (RB)
- if a < b then c <- 0b100
- else if a > b then c <- 0b010
- else c <- 0b001
- CR[4*BF+32:4*BF+35] <- c || XER[SO]
-
-Special Registers Altered:
-
- CR field BF
-
-# Compare Logical Immediate
-
-D-Form
-
-* cmpli BF,L,RA,UI
-
-Pseudo-code:
-
- if L = 0 then a <- [0]*32 || (RA)[32:63]
- else a <- (RA)
- if a <u ([0]*48 || UI) then c <- 0b100
- else if a >u ([0]*48 || UI) then c <- 0b010
- else c <- 0b001
- CR[4*BF+32:4*BF+35] <- c || XER[SO]
-
-Special Registers Altered:
-
- CR field BF
-
-# Compare Logical
-
-X-Form
-
-* cmpl BF,L,RA,RB
-
-Pseudo-code:
-
- if L = 0 then
- a <- [0]*32 || (RA)[32:63]
- b <- [0]*32 || (RB)[32:63]
- else
- a <- (RA)
- b <- (RB)
- if a <u b then c <- 0b100
- else if a >u b then c <- 0b010
- else c <- 0b001
- CR[4*BF+32:4*BF+35] <- c || XER[SO]
-
-Special Registers Altered:
-
- CR field BF
-
-# Compare Ranged Byte
-
-X-Form
-
-* cmprb BF,L,RA,RB
-
-Pseudo-code:
-
- src1 <- EXTZ((RA)[56:63])
- src21hi <- EXTZ((RB)[32:39])
- src21lo <- EXTZ((RB)[40:47])
- src22hi <- EXTZ((RB)[48:55])
- src22lo <- EXTZ((RB)[56:63])
- if L=0 then
- in_range <- (src22lo <= src1) & (src1 <= src22hi)
- else
- in_range <- (((src21lo <= src1) & (src1 <= src21hi)) |
- ((src22lo <= src1) & (src1 <= src22hi)))
- CR[4*BF+32] <- 0b0
- CR[4*BF+33] <- in_range
- CR[4*BF+34] <- 0b0
- CR[4*BF+35] <- 0b0
-
-Special Registers Altered:
-
- CR field BF
-
-# Compare Equal Byte
-
-X-Form
-
-* cmpeqb BF,RA,RB
-
-Pseudo-code:
-
- src1 <- GPR[RA]
- src1 <- src1[56:63]
- match <- ((src1 = (RB)[00:07]) |
- (src1 = (RB)[08:15]) |
- (src1 = (RB)[16:23]) |
- (src1 = (RB)[24:31]) |
- (src1 = (RB)[32:39]) |
- (src1 = (RB)[40:47]) |
- (src1 = (RB)[48:55]) |
- (src1 = (RB)[56:63]))
- CR[4*BF+32] <- 0b0
- CR[4*BF+33] <- match
- CR[4*BF+34] <- 0b0
- CR[4*BF+35] <- 0b0
-
-Special Registers Altered:
-
- CR field BF
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 2.5.1 Condition Register Logical Instructions Pages 40 - 41 -->
-
-<!-- The Condition Register Logical instructions have preferred forms; see Section -->
-<!-- 1.9.1. -->
-
-<!-- In the preferred forms, the BT and BB fields satisfy the following rule: -->
-
-<!-- * The bit specified by BT is in the same Condition Register field as the bit -->
-<!-- specified by BB. -->
-
-# Condition Register AND
-
-XL-Form
-
-* crand BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- CR[BA+32] & CR[BB+32]
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register NAND
-
-XL-Form
-
-* crnand BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register OR
-
-XL-Form
-
-* cror BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- CR[BA+32] | CR[BB+32]
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register XOR
-
-XL-Form
-
-* crxor BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- CR[BA+32] ^ CR[BB+32]
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register NOR
-
-XL-Form
-
-* crnor BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register Equivalent
-
-XL-Form
-
-* creqv BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- ¬(CR[BA+32] ^ CR[BB+32])
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register AND with Complement
-
-XL-Form
-
-* crandc BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- CR[BA+32] & ¬CR[BB+32]
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Condition Register OR with Complement
-
-XL-Form
-
-* crorc BT,BA,BB
-
-Pseudo-code:
-
- CR[BT+32] <- CR[BA+32] | ¬CR[BB+32]
-
-Special Registers Altered:
-
- CR[BT+32]
-
-# Move Condition Register Field
-
-XL-Form
-
-* mcrf BF,BFA
-
-Pseudo-code:
-
- CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]
-
-Special Registers Altered:
-
- CR field BF
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.9 Fixed-point arithmetic instructions. Pages 67 - 83 -->
-
-# Add Immediate
-
-D-Form
-
-* addi RT,RA,SI
-
-Pseudo-code:
-
- RT <- (RA|0) + EXTS(SI)
-
-Special Registers Altered:
-
- None
-
-# Add Immediate Shifted
-
-D-Form
-
-* addis RT,RA,SI
-
-Pseudo-code:
-
- RT <- (RA|0) + EXTS(SI || [0]*16)
-
-Special Registers Altered:
-
- None
-
-# Add PC Immediate Shifted
-
-DX-Form
-
-* addpcis RT,D
-
-Pseudo-code:
-
- D <- d0||d1||d2
- RT <- NIA + EXTS(D || [0]*16)
-
-Special Registers Altered:
-
- None
-
-# Add
-
-XO-Form
-
-* add RT,RA,RB (OE=0 Rc=0)
-* add. RT,RA,RB (OE=0 Rc=1)
-* addo RT,RA,RB (OE=1 Rc=0)
-* addo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- (RA) + (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Subtract From
-
-XO-Form
-
-* subf RT,RA,RB (OE=0 Rc=0)
-* subf. RT,RA,RB (OE=0 Rc=1)
-* subfo RT,RA,RB (OE=1 Rc=0)
-* subfo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- ¬(RA) + (RB) + 1
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Add Immediate Carrying
-
-D-Form
-
-* addic RT,RA,SI
-
-Pseudo-code:
-
- RT <- (RA) + EXTS(SI)
-
-Special Registers Altered:
-
- CA CA32
-
-# Add Immediate Carrying and Record
-
-D-Form
-
-* addic. RT,RA,SI
-
-Pseudo-code:
-
- RT <- (RA) + EXTS(SI)
-
-Special Registers Altered:
-
- CR0 CA CA32
-
-# Subtract From Immediate Carrying
-
-D-Form
-
-* subfic RT,RA,SI
-
-Pseudo-code:
-
- RT <- ¬(RA) + EXTS(SI) + 1
-
-Special Registers Altered:
-
- CA CA32
-
-# Add Carrying
-
-XO-Form
-
-* addc RT,RA,RB (OE=0 Rc=0)
-* addc. RT,RA,RB (OE=0 Rc=1)
-* addco RT,RA,RB (OE=1 Rc=0)
-* addco. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- (RA) + (RB)
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Subtract From Carrying
-
-XO-Form
-
-* subfc RT,RA,RB (OE=0 Rc=0)
-* subfc. RT,RA,RB (OE=0 Rc=1)
-* subfco RT,RA,RB (OE=1 Rc=0)
-* subfco. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- ¬(RA) + (RB) + 1
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Add Extended
-
-XO-Form
-
-* adde RT,RA,RB (OE=0 Rc=0)
-* adde. RT,RA,RB (OE=0 Rc=1)
-* addeo RT,RA,RB (OE=1 Rc=0)
-* addeo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- (RA) + (RB) + CA
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Subtract From Extended
-
-XO-Form
-
-* subfe RT,RA,RB (OE=0 Rc=0)
-* subfe. RT,RA,RB (OE=0 Rc=1)
-* subfeo RT,RA,RB (OE=1 Rc=0)
-* subfeo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- ¬(RA) + (RB) + CA
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Add to Minus One Extended
-
-XO-Form
-
-* addme RT,RA (OE=0 Rc=0)
-* addme. RT,RA (OE=0 Rc=1)
-* addmeo RT,RA (OE=1 Rc=0)
-* addmeo. RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- (RA) + CA - 1
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Subtract From Minus One Extended
-
-XO-Form
-
-* subfme RT,RA (OE=0 Rc=0)
-* subfme. RT,RA (OE=0 Rc=1)
-* subfmeo RT,RA (OE=1 Rc=0)
-* subfmeo. RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- ¬(RA) + CA - 1
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Add Extended using alternate carry bit
-
-Z23-Form
-
-* addex RT,RA,RB,CY
-
-Pseudo-code:
-
- if CY=0 then RT <- (RA) + (RB) + OV
-
-Special Registers Altered:
-
- OV OV32 (if CY=0 )
-
-# Subtract From Zero Extended
-
-XO-Form
-
-* subfze RT,RA (OE=0 Rc=0)
-* subfze. RT,RA (OE=0 Rc=1)
-* subfzeo RT,RA (OE=1 Rc=0)
-* subfzeo. RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- ¬(RA) + CA
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Add to Zero Extended
-
-XO-Form
-
-* addze RT,RA (OE=0 Rc=0)
-* addze. RT,RA (OE=0 Rc=1)
-* addzeo RT,RA (OE=1 Rc=0)
-* addzeo. RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- (RA) + CA
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Negate
-
-XO-Form
-
-* neg RT,RA (OE=0 Rc=0)
-* neg. RT,RA (OE=0 Rc=1)
-* nego RT,RA (OE=1 Rc=0)
-* nego. RT,RA (OE=1 Rc=1)
-
-Pseudo-code:
-
- RT <- ¬(RA) + 1
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Multiply Low Immediate
-
-D-Form
-
-* mulli RT,RA,SI
-
-Pseudo-code:
-
- prod[0:127] <- MULS((RA), EXTS(SI))
- RT <- prod[64:127]
-
-Special Registers Altered:
-
- None
-
-# Multiply High Word
-
-XO-Form
-
-* mulhw RT,RA,RB (Rc=0)
-* mulhw. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
- RT[32:63] <- prod[0:31]
- RT[0:31] <- undefined(prod[0:31])
-
-Special Registers Altered:
-
- CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-
-# Multiply Low Word
-
-XO-Form
-
-* mullw RT,RA,RB (OE=0 Rc=0)
-* mullw. RT,RA,RB (OE=0 Rc=1)
-* mullwo RT,RA,RB (OE=1 Rc=0)
-* mullwo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
- RT <- prod
- overflow <- ((prod[0:32] != [0]*33) &
- (prod[0:32] != [1]*33))
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Multiply High Word Unsigned
-
-XO-Form
-
-* mulhwu RT,RA,RB (Rc=0)
-* mulhwu. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- prod[0:63] <- (RA)[32:63] * (RB)[32:63]
- RT[32:63] <- prod[0:31]
- RT[0:31] <- undefined(prod[0:31])
-
-Special Registers Altered:
-
- CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
-
-# Divide Word
-
-XO-Form
-
-* divw RT,RA,RB (OE=0 Rc=0)
-* divw. RT,RA,RB (OE=0 Rc=1)
-* divwo RT,RA,RB (OE=1 Rc=0)
-* divwo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:31] <- (RA)[32:63]
- divisor[0:31] <- (RB) [32:63]
- if (((dividend = 0x8000_0000) &
- (divisor = [1]*32)) |
- (divisor = [0]*32)) then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT[32:63] <- DIVS(dividend, divisor)
- RT[0:31] <- undefined([0]*32)
- overflow <- 0
-
-Special Registers Altered:
-
- CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Divide Word Unsigned
-
-XO-Form
-
-* divwu RT,RA,RB (OE=0 Rc=0)
-* divwu. RT,RA,RB (OE=0 Rc=1)
-* divwuo RT,RA,RB (OE=1 Rc=0)
-* divwuo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:31] <- (RA)[32:63]
- divisor[0:31] <- (RB)[32:63]
- if divisor != 0 then
- RT[32:63] <- dividend / divisor
- RT[0:31] <- undefined([0]*32)
- overflow <- 0
- else
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
-
-Special Registers Altered:
-
- CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Divide Word Extended
-
-XO-Form
-
-* divwe RT,RA,RB (OE=0 Rc=0)
-* divwe. RT,RA,RB (OE=0 Rc=1)
-* divweo RT,RA,RB (OE=1 Rc=0)
-* divweo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:63] <- (RA)[32:63] || [0]*32
- divisor[0:63] <- EXTS64((RB)[32:63])
- if (((dividend = 0x8000_0000_0000_0000) &
- (divisor = [1]*64)) |
- (divisor = [0]*64)) then
- overflow <- 1
- else
- result <- DIVS(dividend, divisor)
- result32[0:63] <- EXTS64(result[32:63])
- if (result32 = result) then
- RT[32:63] <- result[32:63]
- RT[0:31] <- undefined([0]*32)
- overflow <- 0
- else
- overflow <- 1
- if overflow = 1 then
- RT[0:63] <- undefined([0]*64)
-
-Special Registers Altered:
-
- CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Divide Word Extended Unsigned
-
-XO-Form
-
-* divweu RT,RA,RB (OE=0 Rc=0)
-* divweu. RT,RA,RB (OE=0 Rc=1)
-* divweuo RT,RA,RB (OE=1 Rc=0)
-* divweuo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:63] <- (RA)[32:63] || [0]*32
- divisor[0:63] <- [0]*32 || (RB)[32:63]
- if (divisor = [0]*64) then
- overflow <- 1
- else
- result <- dividend / divisor
- if RA[32:63] <u RB[32:63] then
- RT[32:63] <- result[32:63]
- RT[0:31] <- undefined([0]*32)
- overflow <- 0
- else
- overflow <- 1
- if overflow = 1 then
- RT[0:63] <- undefined([0]*64)
-
-Special Registers Altered:
-
- CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Modulo Signed Word
-
-X-Form
-
-* modsw RT,RA,RB
-
-Pseudo-code:
-
- dividend[0:31] <- (RA)[32:63]
- divisor[0:31] <- (RB)[32:63]
- if (((dividend = 0x8000_0000) &
- (divisor = [1]*32)) |
- (divisor = [0]*32)) then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT[0:63] <- EXTS64(MODS(dividend, divisor))
- RT[0:31] <- undefined(RT[0:31])
- overflow <- 0
-
-Special Registers Altered:
-
- None
-
-# Modulo Unsigned Word
-
-X-Form
-
-* moduw RT,RA,RB
-
-Pseudo-code:
-
- dividend[0:31] <- (RA) [32:63]
- divisor [0:31] <- (RB) [32:63]
- if divisor = [0]*32 then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT[32:63] <- dividend % divisor
- RT[0:31] <- undefined([0]*32)
- overflow <- 0
-
-Special Registers Altered:
-
- None
-
-# Deliver A Random Number
-
-X-Form
-
-* darn RT,L3
-
-Pseudo-code:
-
- RT <- random(L3)
-
-Special Registers Altered:
-
- none
-
-# Multiply Low Doubleword
-
-XO-Form
-
-* mulld RT,RA,RB (OE=0 Rc=0)
-* mulld. RT,RA,RB (OE=0 Rc=1)
-* mulldo RT,RA,RB (OE=1 Rc=0)
-* mulldo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- prod[0:127] <- MULS((RA), (RB))
- RT <- prod[64:127]
- overflow <- ((prod[0:64] != [0]*65) &
- (prod[0:64] != [1]*65))
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Multiply High Doubleword
-
-XO-Form
-
-* mulhd RT,RA,RB (Rc=0)
-* mulhd. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- prod[0:127] <- MULS((RA), (RB))
- RT <- prod[0:63]
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Multiply High Doubleword Unsigned
-
-XO-Form
-
-* mulhdu RT,RA,RB (Rc=0)
-* mulhdu. RT,RA,RB (Rc=1)
-
-Pseudo-code:
-
- prod[0:127] <- (RA) * (RB)
- RT <- prod[0:63]
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Multiply-Add High Doubleword VA-Form
-
-VA-Form
-
-* maddhd RT,RA.RB,RC
-
-Pseudo-code:
-
- prod[0:127] <- MULS((RA), (RB))
- sum[0:127] <- prod + EXTS(RC)
- RT <- sum[0:63]
-
-Special Registers Altered:
-
- None
-
-# Multiply-Add High Doubleword Unsigned
-
-VA-Form
-
-* maddhdu RT,RA.RB,RC
-
-Pseudo-code:
-
- prod[0:127] <- (RA) * (RB)
- sum[0:127] <- prod + EXTZ(RC)
- RT <- sum[0:63]
-
-Special Registers Altered:
-
- None
-
-# Multiply-Add Low Doubleword
-
-VA-Form
-
-* maddld RT,RA.RB,RC
-
-Pseudo-code:
-
- prod[0:127] <- MULS((RA), (RB))
- sum[0:127] <- prod + EXTS(RC)
- RT <- sum[64:127]
-
-Special Registers Altered:
-
- None
-
-# Divide Doubleword
-
-XO-Form
-
-* divd RT,RA,RB (OE=0 Rc=0)
-* divd. RT,RA,RB (OE=0 Rc=1)
-* divdo RT,RA,RB (OE=1 Rc=0)
-* divdo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:63] <- (RA)
- divisor[0:63] <- (RB)
- if (((dividend = 0x8000_0000_0000_0000) &
- (divisor = [1]*64)) |
- (divisor = [0]*64)) then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT <- DIVS(dividend, divisor)
- overflow <- 0
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Divide Doubleword Unsigned
-
-XO-Form
-
-* divdu RT,RA,RB (OE=0 Rc=0)
-* divdu. RT,RA,RB (OE=0 Rc=1)
-* divduo RT,RA,RB (OE=1 Rc=0)
-* divduo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:63] <- (RA)
- divisor[0:63] <- (RB)
- if (divisor = [0]*64) then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT <- dividend / divisor
- overflow <- 0
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Divide Doubleword Extended
-
-XO-Form
-
-* divde RT,RA,RB (OE=0 Rc=0)
-* divde. RT,RA,RB (OE=0 Rc=1)
-* divdeo RT,RA,RB (OE=1 Rc=0)
-* divdeo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:127] <- (RA) || [0]*64
- divisor[0:127] <- EXTS128((RB))
- if (((dividend = 0x8000_0000_0000_0000_0000_0000_0000_0000) &
- (divisor = [1]*128)) |
- (divisor = [0]*128)) then
- overflow <- 1
- else
- result <- DIVS(dividend, divisor)
- result64[0:127] <- EXTS128(result[64:127])
- if (result64 = result) then
- RT <- result[64:127]
- overflow <- 0
- else
- overflow <- 1
- if overflow = 1 then
- RT[0:63] <- undefined([0]*64)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Divide Doubleword Extended Unsigned
-
-XO-Form
-
-* divdeu RT,RA,RB (OE=0 Rc=0)
-* divdeu. RT,RA,RB (OE=0 Rc=1)
-* divdeuo RT,RA,RB (OE=1 Rc=0)
-* divdeuo. RT,RA,RB (OE=1 Rc=1)
-
-Pseudo-code:
-
- dividend[0:127] <- (RA) || [0]*64
- divisor[0:127] <- [0]*64 || (RB)
- if divisor = [0]*128 then
- overflow <- 1
- else
- result <- dividend / divisor
- if (RA) <u (RB) then
- RT <- result[64:127]
- overflow <- 0
- else
- overflow <- 1
- if overflow = 1 then
- RT[0:63] <- undefined([0]*64)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
-
-# Modulo Signed Doubleword
-
-X-Form
-
-* modsd RT,RA,RB
-
-Pseudo-code:
-
- dividend <- (RA)
- divisor <- (RB)
- if (((dividend = 0x8000_0000_0000_0000) &
- (divisor = [1]*64)) |
- (divisor = [0]*64)) then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT <- MODS(dividend, divisor)
- overflow <- 0
-
-Special Registers Altered:
-
- None
-
-# Modulo Unsigned Doubleword
-
-X-Form
-
-* modud RT,RA,RB
-
-Pseudo-code:
-
- dividend <- (RA)
- divisor <- (RB)
- if (divisor = [0]*64) then
- RT[0:63] <- undefined([0]*64)
- overflow <- 1
- else
- RT <- dividend % divisor
- overflow <- 0
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 4.4.1 Fixed-Point Load and Store Caching Inhibited Instructions. Pages 965 - 967 -->
-
-<!-- The storage accesses caused by the instructions described in this section are -->
-<!-- performed as though the specified storage location is Caching Inhibited and -->
-<!-- Guarded. The instructions can be executed only in hypervisor state. Software -->
-<!-- must ensure that the specified storage location is not in the caches. If the -->
-<!-- specified storage location is in a cache, the results are undefined. -->
-
-
-# Load Byte and Zero Caching Inhibited Indexed
-
-X-Form
-
-* lbzcix RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- [0] * 56 || MEM(EA, 1)
-
-Special Registers Altered:
-
- None
-
-# Load Halfword and Zero Caching Inhibited Indexed
-
-X-Form
-
-* lhzcix RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- [0] * 48 || MEM(EA, 2)
-
-Special Registers Altered:
-
- None
-
-# Load Word and Zero Caching Inhibited Indexed
-
-X-Form
-
-* lwzcix RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- [0] * 32 || MEM(EA, 4)
-
-Special Registers Altered:
-
- None
-
-# Load Doubleword Caching Inhibited Indexed
-
-X-Form
-
-* ldcix RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- MEM(EA, 8)
-
-Special Registers Altered:
-
- None
-
-# Store Byte Caching Inhibited Indexed
-
-X-Form
-
-* stbcix RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 1) <- (RS)[56:63]
-
-Special Registers Altered:
-
- None
-
-# Store Halfword Caching Inhibited Indexed
-
-X-Form
-
-* sthcix RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 2) <- (RS)[48:63]
-
-Special Registers Altered:
-
- None
-
-# Store Word Caching Inhibited Indexed
-
-X-Form
-
-* stwcix RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 4) <- (RS)[32:63]
-
-Special Registers Altered:
-
- None
-
-# Store Doubleword Caching Inhibited Indexed
-
-X-Form
-
-* stdcix RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 8) <- (RS)
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- This defines instructions that load from RAM to a register -->
-
-<!-- Note that these pages also define equivalent store instructions, -->
-<!-- these are described in fixedstore.mdwn -->
-
-<!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
-<!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
-<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
-<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
-<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
-<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
-<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
-
-
-
-<!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
-
-<!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
-<!-- into register RT. -->
-
-<!-- Many of the Load instructions have an “update” form, in which register RA is -->
-<!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
-<!-- effective address is placed into register RA and the storage element (byte, -->
-<!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
-
-
-# Load Byte and Zero
-
-D-Form
-
-* lbz RT,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- RT <- [0]*56 || MEM(EA, 1)
-
-Special Registers Altered:
-
- None
-
-# Load Byte and Zero Indexed
-
-X-Form
-
-* lbzx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- [0] * 56 || MEM(EA, 1)
-
-Special Registers Altered:
-
- None
-
-# Load Byte and Zero with Update
-
-D-Form
-
-* lbzu RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- RT <- [0] * 56 || MEM(EA, 1)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Byte and Zero with Update Indexed
-
-X-Form
-
-* lbzux RT,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- RT <- [0] * 56 || MEM(EA, 1)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Halfword and Zero
-
-D-Form
-
-* lhz RT,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- RT <- [0] * 48 || MEM(EA, 2)
-
-Special Registers Altered:
-
- None
-
-# Load Halfword and Zero Indexed
-
-X-Form
-
-* lhzx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- [0] * 48 || MEM(EA, 2)
-
-Special Registers Altered:
-
- None
-
-# Load Halfword and Zero with Update
-
-D-Form
-
-* lhzu RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- RT <- [0] * 48 || MEM(EA, 2)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Halfword and Zero with Update Indexed
-
-X-Form
-
-* lhzux RT,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- RT <- [0] * 48 || MEM(EA, 2)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Halfword Algebraic
-
-D-Form
-
-* lha RT,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- RT <- EXTS(MEM(EA, 2))
-
-Special Registers Altered:
-
- None
-
-# Load Halfword Algebraic Indexed
-
-X-Form
-
-* lhax RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- EXTS(MEM(EA, 2))
-
-Special Registers Altered:
-
- None
-
-# Load Halfword Algebraic with Update
-
-D-Form
-
-* lhau RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- RT <- EXTS(MEM(EA, 2))
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Halfword Algebraic with Update Indexed
-
-X-Form
-
-* lhaux RT,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- RT <- EXTS(MEM(EA, 2))
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Word and Zero
-
-D-Form
-
-* lwz RT,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- RT <- [0] * 32 || MEM(EA, 4)
-
-Special Registers Altered:
-
- None
-
-# Load Word and Zero Indexed
-
-X-Form
-
-* lwzx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- [0] * 32 || MEM(EA, 4)
-
-Special Registers Altered:
-
- None
-
-# Load Word and Zero with Update
-
-D-Form
-
-* lwzu RT,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- RT <- [0]*32 || MEM(EA, 4)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Word and Zero with Update Indexed
-
-X-Form
-
-* lwzux RT,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- RT <- [0] * 32 || MEM(EA, 4)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Word Algebraic
-
-DS-Form
-
-* lwa RT,DS(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(DS || 0b00)
- RT <- EXTS(MEM(EA, 4))
-
-Special Registers Altered:
-
- None
-
-# Load Word Algebraic Indexed
-
-X-Form
-
-* lwax RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- EXTS(MEM(EA, 4))
-
-Special Registers Altered:
-
- None
-
-# Load Word Algebraic with Update Indexed
-
-X-Form
-
-* lwaux RT,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- RT <- EXTS(MEM(EA, 4))
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Doubleword
-
-DS-Form
-
-* ld RT,DS(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(DS || 0b00)
- RT <- MEM(EA, 8)
-
-Special Registers Altered:
-
- None
-
-# Load Doubleword Indexed
-
-X-Form
-
-* ldx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- RT <- MEM(EA, 8)
-
-Special Registers Altered:
-
- None
-
-# Load Doubleword with Update Indexed
-
-DS-Form
-
-* ldu RT,DS(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(DS || 0b00)
- RT <- MEM(EA, 8)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Load Doubleword with Update Indexed
-
-X-Form
-
-* ldux RT,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- RT <- MEM(EA, 8)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-<!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
-
-<!-- The contents of register RS are stored into the byte, halfword, word, or -->
-<!-- doubleword in storage addressed by EA. -->
-
-<!-- Many of the Store instructions have an “update” form, in which register RA is -->
-<!-- updated with the effective address. For these forms, the following rules apply. -->
-
-<!-- If RA!=0, the effective address is placed into register RA. -->
-
-<!-- If RS=RA, the contents of register RS are copied to the target storage element -->
-<!-- and then EA is placed into RA (RS). -->
-
-<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
-
-<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
-
-<!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
-<!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
-<!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
-<!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
-<!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
-<!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
-<!-- by EA. -->
-
-# Load Quadword
-
-DQ-Form
-
-* lq RTp,DQ(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(DQ || 0b0000)
- RTp <- MEM(EA, 16)
-
-Special Registers Altered:
-
- None
-
-<!-- MISSING stq -->
-
-<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
-
-# Load Halfword Byte-Reverse Indexed
-
-X-Form
-
-* lhbrx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- load_data <- MEM(EA, 2)
- RT <- [0]*48 || load_data[8:15] || load_data[0:7]
-
-Special Registers Altered:
-
- None
-
-<!-- MISSING sthbrx -->
-
-# Load Word Byte-Reverse Indexed
-
-X-Form
-
-* lwbrx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- load_data <- MEM(EA, 4)
- RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
- || load_data[8:15] || load_data[0:7])
-
-Special Registers Altered:
-
- None
-
-<!-- MISSING stwbrx -->
-
-
-<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
-
-# Load Doubleword Byte-Reverse Indexed
-
-X-Form
-
-* ldbrx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- load_data <- MEM(EA, 8)
- RT <- (load_data[56:63] || load_data[48:55]
- || load_data[40:47] || load_data[32:39]
- || load_data[24:31] || load_data[16:23]
- || load_data[8:15] || load_data[0:7])
-
-Special Registers Altered:
-
- None
-
-<!-- MISSING stdbrx -->
-
-<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
-
-# Load Multiple Word
-
-DQ-Form
-
-* lmw RT,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- r <- RT
- do while r <= 31
- GPR(r) <- [0]*32 || MEM(EA, 4)
- r <- r + 1
- EA <- EA + 4
-
-Special Registers Altered:
-
- None
-
-<!-- MISSING stmw -->
-
-
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.13 Fixed-Point Logical Instructions page 92 - 100 -->
-
-<!-- The Logical instructions perform bit-parallel operations on 64-bit operands. -->
-
-<!-- The X-form Logical instructions with Rc=1, and the D-form Logical instructions -->
-<!-- andi. and andis., set the first three bits of CR Field 0 as described in -->
-<!-- Section 3.3.8, “Other Fixed-Point Instructions” on page 66. The Logical -->
-<!-- instructions do not change the SO, OV, OV32, CA, and CA32 bits in the XER. -->
-
-
-# AND Immediate
-
-D-Form
-
-* andi. RA,RS,UI
-
-Pseudo-code:
-
- RA <- (RS) & ([0]*48 || UI)
-
-Special Registers Altered:
-
- CR0
-
-# OR Immediate
-
-D-Form
-
-* ori RA,RS,UI
-
-Pseudo-code:
-
- RA <- (RS) | ([0]*48 || UI)
-
-Special Registers Altered:
-
- None
-
-# AND Immediate Shifted
-
-D-Form
-
-* andis. RA,RS,UI
-
-Pseudo-code:
-
- RA <- (RS) & ([0]*32 || UI || [0]*16)
-
-Special Registers Altered:
-
- CR0
-
-# OR Immediate Shifted
-
-D-Form
-
-* oris RA,RS,UI
-
-Pseudo-code:
-
- RA <- (RS) | ([0]*32 || UI || [0]*16)
-
-Special Registers Altered:
-
- None
-
-# XOR Immediate Shifted
-
-D-Form
-
-* xoris RA,RS,UI
-
-Pseudo-code:
-
- RA <- (RS) ^ ([0]*32 || UI || [0]*16)
-
-Special Registers Altered:
-
- None
-
-# XOR Immediate
-
-D-Form
-
-* xori RA,RS,UI
-
-Pseudo-code:
-
- RA <- (RS) ^ ([0]*48 || UI)
-
-Special Registers Altered:
-
- None
-
-# AND
-
-X-Form
-
-* and RA,RS,RB (Rc=0)
-* and. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- (RS) & (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# OR
-
-X-Form
-
-* or RA,RS,RB (Rc=0)
-* or. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- (RS) | (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# XOR
-
-X-Form
-
-* xor RA,RS,RB (Rc=0)
-* xor. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- (RS) ^ (RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# NAND
-
-X-Form
-
-* nand RA,RS,RB (Rc=0)
-* nand. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- ¬((RS) & (RB))
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# NOR
-
-X-Form
-
-* nor RA,RS,RB (Rc=0)
-* nor. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- ¬((RS) | (RB))
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Equivalent
-
-X-Form
-
-* eqv RA,RS,RB (Rc=0)
-* eqv. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- ¬((RS) ^ (RB))
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# AND with Complement
-
-X-Form
-
-* andc RA,RS,RB (Rc=0)
-* andc. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- (RS) & ¬(RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# OR with Complement
-
-X-Form
-
-* orc RA,RS,RB (Rc=0)
-* orc. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- RA <- (RS) | ¬(RB)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Extend Sign Byte
-
-X-Form
-
-* extsb RA,RS (Rc=0)
-* extsb. RA,RS (Rc=1)
-
-Pseudo-code:
-
- s <- (RS)[56]
- RA[56:63] <- (RS)[56:63]
- RA[0:55] <- [s]*56
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Extend Sign Halfword
-
-X-Form
-
-* extsh RA,RS (Rc=0)
-* extsh. RA,RS (Rc=1)
-
-Pseudo-code:
-
- s <- (RS)[48]
- RA[48:63] <- (RS)[48:63]
- RA[0:47] <- [s]*48
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Count Leading Zeros Word
-
-X-Form
-
-* cntlzw RA,RS (Rc=0)
-* cntlzw. RA,RS (Rc=1)
-
-Pseudo-code:
-
- n <- 32
- do while n < 64
- if (RS)[n] = 1 then
- leave
- n <- n + 1
- RA <- n - 32
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Count Trailing Zeros Word
-
-X-Form
-
-* cnttzw RA,RS (Rc=0)
-* cnttzw. RA,RS (Rc=1)
-
-Pseudo-code:
-
- n <- 0
- do while n < 32
- if (RS)[63-n] = 0b1 then
- leave
- n <- n + 1
- RA <- EXTZ64(n)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Compare Bytes
-
-X-Form
-
-* cmpb RA,RS,RB
-
-Pseudo-code:
-
- do n = 0 to 7
- if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
- RA[8*n:8* n+7] <- [1]*8
- else
- RA[8*n:8* n+7] <- [0]*8
-
-Special Registers Altered:
-
- None
-
-# Population Count Bytes
-
-X-Form
-
-* popcntb RA, RS
-
-Pseudo-code:
-
- do i = 0 to 7
- n <- 0
- do j = 0 to 7
- if (RS)[(i*8)+j] = 1 then
- n <- n+1
- RA[(i*8):(i*8)+7] <- n
-
-Special Registers Altered:
-
- None
-
-# Population Count Words
-
-X-Form
-
-* popcntw RA, RS
-
-Pseudo-code:
-
- do i = 0 to 1
- n <- 0
- do j = 0 to 31
- if (RS)[(i*32)+j] = 1 then
- n <- n+1
- RA[(i*32):(i*32)+31] <- n
-
-Special Registers Altered:
-
- None
-
-# Parity Doubleword
-
-X-Form
-
-* prtyd RA,RS
-
-Pseudo-code:
-
- s <- 0
- do i = 0 to 7
- s <- s ^ (RS)[i*8+7]
- RA <- [0] * 63 || s
-
-Special Registers Altered:
-
- None
-
-# Parity Word
-
-X-Form
-
-* prtyw RA,RS
-
-Pseudo-code:
-
- s <- 0
- t <- 0
- do i = 0 to 3
- s <- s ^ (RS)[i*8+7]
- do i = 4 to 7
- t <- t ^ (RS)[i*8+7]
- RA[0:31] <- [0]*31 || s
- RA[32:63] <- [0]*31 || t
-
-Special Registers Altered:
-
- None
-
-# Extend Sign Word
-
-X-Form
-
-* extsw RA,RS (Rc=0)
-* extsw. RA,RS (Rc=1)
-
-Pseudo-code:
-
- s <- (RS)[32]
- RA[32:63] <- (RS)[32:63]
- RA[0:31] <- [s]*32
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Population Count Doubleword
-
-X-Form
-
-* popcntd RA, RS
-
-Pseudo-code:
-
- n <- 0
- do i = 0 to 63
- if (RS)[i] = 1 then
- n <- n+1
- RA <- n
-
-Special Registers Altered:
-
- None
-
-# Count Leading Zeros Doubleword
-
-X-Form
-
-* cntlzd RA,RS (Rc=0)
-* cntlzd. RA,RS (Rc=1)
-
-Pseudo-code:
-
- n <- 0
- do while n < 64
- if (RS)[n] = 1 then
- leave
- n <- n + 1
- RA <- n
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Count Trailing Zeros Doubleword
-
-X-Form
-
-* cnttzd RA,RS (Rc=0)
-* cnttzd. RA,RS (Rc=1)
-
-Pseudo-code:
-
- n <- 0
- do while n < 64
- if (RS)[63-n] = 0b1 then
- leave
- n <- n + 1
- RA <- EXTZ64(n)
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Bit Permute Doubleword
-
-X-Form
-
-* bpermd RA,RS,RB]
-
-Pseudo-code:
-
- perm <- [0] * 8
- for i = 0 to 7
- index <- (RS)[8*i:8*i+7]
- if index < 64 then
- perm[i] <- (RB)[index]
- else
- perm[i] <- 0
- RA <- [0]*56 || perm[0:7]
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.14 Fixed-Point Rotate and Shift Instructions pages 101 - 110 -->
-<!-- Section 3.3.14.1 Fixed-Point Rotate Instructions pages 101 - 106 -->
-<!-- Section 3.3.14.2 Fixed-Point Shift Instructions pages 107 - 110 -->
-
-<!-- The Fixed-Point Facility performs rotation operations on data from a GPR and -->
-<!-- returns the result, or a portion of the result, to a GPR. -->
-
-
-<!-- Section 3.3.14.1 Fixed-Point Rotate Instructions pages 101 - 106 -->
-
-# Rotate Left Word Immediate then AND with Mask
-
-M-Form
-
-* rlwinm RA,RS,SH,MB,ME (Rc=0)
-* rlwinm. RA,RS,SH,MB,ME (Rc=1)
-
-Pseudo-code:
-
- n <- SH
- r <- ROTL32((RS)[32:63], n)
- m <- MASK(MB+32, ME+32)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Word then AND with Mask
-
-M-Form
-
-* rlwnm RA,RS,RB,MB,ME (Rc=0)
-* rlwnm. RA,RS,RB,MB,ME (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[59:63]
- r <- ROTL32((RS)[32:63], n)
- m <- MASK(MB+32, ME+32)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Word Immediate then Mask Insert
-
-M-Form
-
-* rlwimi RA,RS,SH,MB,ME (Rc=0)
-* rlwimi. RA,RS,SH,MB,ME (Rc=1)
-
-Pseudo-code:
-
- n <- SH
- r <- ROTL32((RS)[32:63], n)
- m <- MASK(MB+32, ME+32)
- RA <- r&m | (RA) & ¬m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Clear Left
-
-MD-Form
-
-* rldicl RA,RS,SH,MB (Rc=0)
-* rldicl. RA,RS,SH,MB (Rc=1)
-
-Pseudo-code:
-
- n <- sh
- r <- ROTL64((RS), n)
- b <- mb[5] || mb[0:4]
- m <- MASK(b, 63)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Clear Right
-
-MD-Form
-
-* rldicr RA,RS,SH,ME (Rc=0)
-* rldicr. RA,RS,SH,ME (Rc=1)
-
-Pseudo-code:
-
- n <- sh
- r <- ROTL64((RS), n)
- e <- me[5] || me[0:4]
- m <- MASK(0, e)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Clear
-
-MD-Form
-
-* rldic RA,RS,SH,MB (Rc=0)
-* rldic. RA,RS,SH,MB (Rc=1)
-
-Pseudo-code:
-
- n <- sh
- r <- ROTL64((RS), n)
- b <- mb[5] || mb[0:4]
- m <- MASK(b, ¬n)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Doubleword then Clear Left
-
-MDS-Form
-
-* rldcl RA,RS,RB,MB (Rc=0)
-* rldcl. RA,RS,RB,MB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[58:63]
- r <- ROTL64((RS), n)
- b <- mb[5] || mb[0:4]
- m <- MASK(b, 63)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Doubleword then Clear Right
-
-MDS-Form
-
-* rldcr RA,RS,RB,ME (Rc=0)
-* rldcr. RA,RS,RB,ME (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[58:63]
- r <- ROTL64((RS), n)
- e <- me[5] || me[0:4]
- m <- MASK(0, e)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Rotate Left Doubleword Immediate then Mask Insert
-
-MD-Form
-
-* rldimi RA,RS,SH,MB (Rc=0)
-* rldimi. RA,RS,SH,MB (Rc=1)
-
-Pseudo-code:
-
- n <- sh
- r <- ROTL64((RS), n)
- b <- mb[5] || mb[0:4]
- m <- MASK(b, ¬n)
- RA <- r&m | (RA)& ¬m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-
-<!-- Section 3.3.14.2 Fixed-Point Shift Instructions pages 107 - 110 -->
-
-# Shift Left Word
-
-X-Form
-
-* slw RA,RS,RB (Rc=0)
-* slw. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[59:63]
- r <- ROTL32((RS)[32:63], n)
- if (RB)[58] = 0 then
- m <- MASK(32, 63-n)
- else m <- [0]*64
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Shift Right Word
-
-X-Form
-
-* srw RA,RS,RB (Rc=0)
-* srw. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[59:63]
- r <- ROTL32((RS)[32:63], 64-n)
- if (RB)[58] = 0 then
- m <- MASK(n+32, 63)
- else m <- [0]*64
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Shift Right Algebraic Word Immediate
-
-X-Form
-
-* srawi RA,RS,SH (Rc=0)
-* srawi. RA,RS,SH (Rc=1)
-
-Pseudo-code:
-
- n <- SH
- r <- ROTL32((RS)[32:63], 64-n)
- m <- MASK(n+32, 63)
- s <- (RS)[32]
- RA <- r&m | ([s]*64)& ¬m
- carry <- s & ((r&¬m)[32:63] != 0)
- CA <- carry
- CA32 <- carry
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
-
-# Shift Right Algebraic Word
-
-X-Form
-
-* sraw RA,RS,RB (Rc=0)
-* sraw. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[59:63]
- r <- ROTL32((RS)[32:63], 64-n)
- if (RB)[58] = 0 then
- m <- MASK(n+32, 63)
- else m <- [0]*64
- s <- (RS)[32]
- RA <- r&m | ([s]*64)& ¬m
- carry <- s & ((r&¬m)[32:63] != 0)
- CA <- carry
- CA32 <- carry
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
-
-# Shift Left Doubleword
-
-X-Form
-
-* sld RA,RS,RB (Rc=0)
-* sld. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[58:63]
- r <- ROTL64((RS), n)
- if (RB)[57] = 0 then
- m <- MASK(0, 63-n)
- else m <- [0]*64
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Shift Right Doubleword
-
-X-Form
-
-* srd RA,RS,RB (Rc=0)
-* srd. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[58:63]
- r <- ROTL64((RS), 64-n)
- if (RB)[57] = 0 then
- m <- MASK(n, 63)
- else m <- [0]*64
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-# Shift Right Algebraic Doubleword Immediate
-
-XS-Form
-
-* sradi RA,RS,SH (Rc=0)
-* sradi. RA,RS,SH (Rc=1)
-
-Pseudo-code:
-
- n <- sh
- r <- ROTL64((RS), 64-n)
- m <- MASK(n, 63)
- s <- (RS)[0]
- RA <- r&m | ([s]*64)& ¬m
- carry <- s & ((r& ¬m) != 0)
- CA <- carry
- CA32 <- carry
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
-
-# Shift Right Algebraic Doubleword
-
-X-Form
-
-* srad RA,RS,RB (Rc=0)
-* srad. RA,RS,RB (Rc=1)
-
-Pseudo-code:
-
- n <- (RB)[58:63]
- r <- ROTL64((RS), 64-n)
- if (RB)[57] = 0 then
- m <- MASK(n, 63)
- else m <- [0]*64
- s <- (RS)[0]
- RA <- r&m | ([s]*64)& ¬m
- carry <- s & ((r&¬m) != 0)
- CA <- carry
- CA32 <- carry
-
-Special Registers Altered:
-
- CA CA32
- CR0 (if Rc=1)
-
-# Extend-Sign Word and Shift Left Immediate
-
-XS-Form
-
-* extswsli RA,RS,SH (Rc=0)
-* extswsli. RA,RS,SH (Rc=1)
-
-Pseudo-code:
-
- n <- sh
- r <- ROTL64(EXTS64(RS[32:63]), n)
- m <- MASK(0, 63-n)
- RA <- r & m
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- This defines instructions that store from a register to RAM -->
-
-<!-- Note that these pages also define equivalent load instructions, -->
-<!-- these are described in fixedload.mdwn -->
-
-<!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
-<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
-<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
-<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
-<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
-<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
-
-<!-- MISSING stbh -->
-<!-- MISSING stbhx -->
-<!-- MISSING stbhu -->
-<!-- MISSING stbhux -->
-<!-- MISSING stbw -->
-<!-- MISSING stbwx -->
-<!-- MISSING stbwu -->
-<!-- MISSING stbwux -->
-
-<!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
-
-# Store Byte
-
-D-Form
-
-* stb RS,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- MEM(EA, 1) <- (RS)[56:63]
-
-Special Registers Altered:
-
- None
-
-# Store Byte Indexed
-
-X-Form
-
-* stbx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 1) <- (RS)[56:63]
-
-Special Registers Altered:
-
- None
-
-# Store Byte with Update
-
-D-Form
-
-* stbu RS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- MEM(EA, 1) <- (RS)[56:63]
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Store Byte with Update Indexed
-
-X-Form
-
-* stbux RS,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- MEM(EA, 1) <- (RS)[56:63]
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Store Halfword
-
-D-Form
-
-* sth RS,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- MEM(EA, 2) <- (RS)[48:63]
-
-Special Registers Altered:
-
- None
-
-# Store Halfword Indexed
-
-X-Form
-
-* sthx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 2) <- (RS)[48:63]
-
-Special Registers Altered:
-
- None
-
-# Store Halfword with Update
-
-D-Form
-
-* sthu RS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- MEM(EA, 2) <- (RS)[48:63]
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Store Halfword with Update Indexed
-
-X-Form
-
-* sthux RS,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- MEM(EA, 2) <- (RS)[48:63]
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Store Word
-
-D-Form
-
-* stw RS,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- MEM(EA, 4) <- (RS)[32:63]
-
-Special Registers Altered:
-
- None
-
-# Store Word Indexed
-
-X-Form
-
-* stwx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 4) <- (RS)[32:63]
-
-Special Registers Altered:
-
- None
-
-# Store Word with Update
-
-D-Form
-
-* stwu RS,D(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(D)
- MEM(EA, 4) <- (RS)[32:63]
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Store Word with Update Indexed
-
-X-Form
-
-* stwux RS,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- MEM(EA, 4) <- (RS)[32:63]
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-
-
-<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
-
-# Store Doubleword
-
-DS-Form
-
-* std RS,DS(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(DS || 0b00)
- MEM(EA, 8) <- (RS)
-
-Special Registers Altered:
-
- None
-
-# Store Doubleword Indexed
-
-X-Form
-
-* stdx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 8) <- (RS)
-
-Special Registers Altered:
-
- None
-
-# Store Doubleword with Update
-
-DS-Form
-
-* stdu RS,DS(RA)
-
-Pseudo-code:
-
- EA <- (RA) + EXTS(DS || 0b00)
- MEM(EA, 8) <- (RS)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-# Store Doubleword with Update Indexed
-
-X-Form
-
-* stdux RS,RA,RB
-
-Pseudo-code:
-
- EA <- (RA) + (RB)
- MEM(EA, 8) <- (RS)
- RA <- EA
-
-Special Registers Altered:
-
- None
-
-
-<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
-
-<!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
-<!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
-<!-- GPR is stored into the doubleword in storage addressed by EA and the -->
-<!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
-<!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
-<!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
-<!-- byte-reversed into the doubleword addressed by EA. -->
-
-
-# Store Quadword
-
-DS-Form
-
-* stq RSp,DS(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(DS || 0b00)
- MEM(EA, 16) <- RSp
-
-Special Registers Altered:
-
- None
-
-<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
-
-# Store Halfword Byte-Reverse Indexed
-
-X-Form
-
-* sthbrx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
-
-Special Registers Altered:
-
- None
-
-# Store Word Byte-Reverse Indexed
-
-X-Form
-
-* stwbrx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
- ||(RS)[32:39])
-
-Special Registers Altered:
-
- None
-
-<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
-
-# Store Doubleword Byte-Reverse Indexed
-
-X-Form
-
-* stdbrx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
- || (RS)[40:47] || (RS)[32:39]
- || (RS)[24:31] || (RS)[16:23]
- || (RS)[8:15] || (RS)[0:7])
-
-Special Registers Altered:
-
- None
-
-
-<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
-
-# Store Multiple Word
-
-D-Form
-
-* stmw RS,D(RA)
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + EXTS(D)
- r <- RS
- do while r <= 31
- MEM(EA, 4) <- GPR(r)[32:63]
- r <- r + 1
- EA <- EA + 4
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.11 Fixed-Point Trap Instructions pages 89 - 91 -->
-
-<!-- The Trap instructions are provided to test for a specified set of conditions. -->
-<!-- If any of the conditions tested by a Trap instruction are met, the system trap -->
-<!-- handler is invoked. If none of the tested conditions are met, instruction -->
-<!-- execution continues normally. -->
-
-# Trap Word Immediate
-
-D-Form
-
-* twi TO,RA,SI
-
-Pseudo-code:
-
- a <- EXTS((RA)[32:63])
- if (a < EXTS(SI)) & TO[0] then TRAP
- if (a > EXTS(SI)) & TO[1] then TRAP
- if (a = EXTS(SI)) & TO[2] then TRAP
- if (a <u EXTS(SI)) & TO[3] then TRAP
- if (a >u EXTS(SI)) & TO[4] then TRAP
-
-Special Registers Altered:
-
- None
-
-# Trap Word
-
-X-Form
-
-* tw TO,RA,RB
-
-Pseudo-code:
-
- a <- EXTS((RA)[32:63])
- b <- EXTS((RB)[32:63])
- if (a < b) & TO[0] then TRAP
- if (a > b) & TO[1] then TRAP
- if (a = b) & TO[2] then TRAP
- if (a <u b) & TO[3] then TRAP
- if (a >u b) & TO[4] then TRAP
-
-Special Registers Altered:
-
- None
-
-# Trap Doubleword Immediate
-
-D-Form
-
-* tdi TO,RA,SI
-
-Pseudo-code:
-
- a <- (RA)
- b <- EXTS(SI)
- if (a < b) & TO[0] then TRAP
- if (a > b) & TO[1] then TRAP
- if (a = b) & TO[2] then TRAP
- if (a <u b) & TO[3] then TRAP
- if (a >u b) & TO[4] then TRAP
-
-Special Registers Altered:
-
- None
-
-# Trap Doubleword
-
-X-Form
-
-* td TO,RA,RB
-
-Pseudo-code:
-
- a <- (RA)
- b <- (RB)
- if (a < b) & TO[0] then TRAP
- if (a > b) & TO[1] then TRAP
- if (a = b) & TO[2] then TRAP
- if (a <u b) & TO[3] then TRAP
- if (a >u b) & TO[4] then TRAP
-
-Special Registers Altered:
-
- None
-
-# Integer Select
-
-A-Form
-
-* isel RT,RA,RB,BC
-
-Pseudo-code:
-
- if CR[BC+32]=1 then RT <- (RA|0)
- else RT <- (RB)
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- These are not described in book 1 -->
-
-# setvl
-
-SVL-Form
-
-* setvl RT, RA, SVi, vs, ms
-* setvl. RT, RA, SVi, vs, ms
-
-Pseudo-code:
-
- VLimm <- SVi + 1
- if vs = 1 then
- if _RA != 0 then
- VL <- (RA|0)[57:63]
- else
- VL <- VLimm[1:7]
- else
- VL <- SVSTATE[7:13]
- if ms = 1 then
- MVL <- VLimm[1:7]
- else
- MVL <- SVSTATE[0:6]
- if VL > MVL then
- VL = MVL
- SVSTATE[0:6] <- MVL
- SVSTATE[7:13] <- VL
- RT <- [0]*57 || VL
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
-
+++ /dev/null
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 4.4.4 Move To/From System Register Instructions pages 970 - 1038 -->
-
-<!-- Section 4.4.4 Move To/From System Register Instructions pages 970 - 1038 -->
-<!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
-<!-- Section 4.3.2 Data Cache Instructions Page 850 -->
-
-<!-- This needs checking again -->
-
-<!-- The Move To Special Purpose Register and Move From Special Purpose Register -->
-<!-- instructions are described in Book I, but only at the level available to an -->
-<!-- application programmer. For example, no mention is made there of registers that -->
-<!-- can be accessed only in privileged state. The descriptions of these instructions -->
-<!-- given below extend the descriptions given in Book I, but do not list Special -->
-<!-- Purpose Registers that are implementation-dependent. In the descriptions of -->
-<!-- these instructions given in below, the “defined” SPR numbers are the SPR -->
-<!-- numbers shown in the Figure 18 for the instruction and the -->
-<!-- implementation-specific SPR numbers that are implemented, and similarly for -->
-<!-- “defined” registers. All other SPR numbers are undefined for the instruction. -->
-<!-- (Implementation-specific SPR numbers that are not implemented are considered to -->
-<!-- be undefined.) When an SPR is defined for mtspr and undefined for mfspr, or -->
-<!-- vice versa, a hyphen appears in the column for the instruction for which the -->
-<!-- SPR number is undefined. -->
-
-
-
-<!-- Page 974 -->
-
-# Move To Special Purpose Register
-
-XFX-Form
-
-* mtspr SPR,RS
-
-Pseudo-code:
-
- n <- spr[5:9] || spr[0:4]
- switch (n)
- case(13): see(Book_III_p974)
- case(808, 809, 810, 811):
- default:
- if length(SPR(n)) = 64 then
- SPR(n) <- (RS)
- else
- SPR(n) <- (RS) [32:63]
-
-Special Registers Altered:
-
- See spec 3.3.17
-
-<!-- Page 975 -->
-
-# Move From Special Purpose Register
-
-XFX-Form
-
-* mfspr RT,SPR
-
-Pseudo-code:
-
- n <- spr[5:9] || spr[0:4]
- switch (n)
- case(129): see(Book_III_p975)
- case(808, 809, 810, 811):
- default:
- if length(SPR(n)) = 64 then
- RT <- SPR(n)
- else
- RT <- [0]*32 || SPR(n)
-
-Special Registers Altered:
-
- None
-
-<!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
-
-# Move to CR from XER Extended
-
-X-Form
-
-* mcrxrx BF
-
-Pseudo-code:
-
- CR[4*BF+32:4*BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
-
-Special Registers Altered:
-
- CR field BF
-
-# Move To One Condition Register Field
-
-XFX-Form
-
-* mtocrf FXM,RS
-
-Pseudo-code:
-
- n <- 7
- do i = 7 to 0
- if FXM[i] = 1 then
- n <- i
- CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
-
-Special Registers Altered:
-
- CR field selected by FXM
-
-# Move To Condition Register Fields
-
-XFX-Form
-
-* mtcrf FXM,RS
-
-Pseudo-code:
-
- do n = 0 to 7
- if FXM[n] = 1 then
- CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
-
-Special Registers Altered:
-
- CR fields selected by mask
-
-# Move From One Condition Register Field
-
-XFX-Form
-
-* mfocrf RT,FXM
-
-Pseudo-code:
-
- done <- 0
- RT <- [0]*64
- do n = 0 to 7
- if (done = 0) & (FXM[n] = 1) then
- RT[4*n+32:4*n+35] <- CR[4*n+32:4*n+35]
- done <- 1
-
-Special Registers Altered:
-
- None
-
-# Move From Condition Register
-
-XFX-Form
-
-* mfcr RT
-
-Pseudo-code:
-
- RT <- [0]*32 || CR
-
-Special Registers Altered:
-
- None
-
-# Set Boolean
-
-X-Form
-
-* setb RT,BFA
-
-Pseudo-code:
-
- if CR[4*BFA+32] = 1 then
- RT <- 0xFFFF_FFFF_FFFF_FFFF
- else if CR[4*BFA+33]=1 then
- RT <- 0x0000_0000_0000_0001
- else
- RT <- 0x0000_0000_0000_0000
-
-Special Registers Altered:
-
- None
-
-<!-- Out of order from the PDF. Page 977 -->
-
-# Move To Machine State Register
-
-X-Form
-
-* mtmsr RS,L1
-
-Pseudo-code:
-
- if L1 = 0 then
- MSR[48] <- (RS)[48] | (RS)[49]
- MSR[58] <- (RS)[58] | (RS)[49]
- MSR[59] <- (RS)[59] | (RS)[49]
- MSR[32:40] <- (RS)[32:40]
- MSR[42:47] <- (RS)[42:47]
- MSR[49:50] <- (RS)[49:50]
- MSR[52:57] <- (RS)[52:57]
- MSR[60:62] <- (RS)[60:62]
- else
- MSR[48] <- (RS)[48]
- MSR[62] <- (RS)[62]
-
-Special Registers Altered:
-
- MSR
-
-# Move To Machine State Register
-
-X-Form
-
-* mtmsrd RS,L1
-
-Pseudo-code:
-
- if L1 = 0 then
- if (MSR[29:31] != 0b010) | ((RS)[29:31] != 0b000) then
- MSR[29:31] <- (RS)[29:31]
- MSR[48] <- (RS)[48] | (RS)[49]
- MSR[58] <- (RS)[58] | (RS)[49]
- MSR[59] <- (RS)[59] | (RS)[49]
- MSR[0:2] <- (RS)[0:2]
- MSR[4:28] <- (RS)[4:28]
- MSR[32:40] <- (RS)[32:40]
- MSR[42:47] <- (RS)[42:47]
- MSR[49:50] <- (RS)[49:50]
- MSR[52:57] <- (RS)[52:57]
- MSR[60:62] <- (RS)[60:62]
- else
- MSR[48] <- (RS)[48]
- MSR[62] <- (RS)[62]
-
-Special Registers Altered:
-
- MSR
-
-# Move From Machine State Register
-
-X-Form
-
-* mfmsr RT
-
-Pseudo-code:
-
- RT <- MSR
-
-Special Registers Altered:
-
- None
-
-<!-- Section 4.3.2 Data Cache Instructions Page 850 -->
-
-# Data Cache Block set to Zero
-
-X-Form
-
-* dcbz RA,RB
-
-Pseudo-code:
-
- if RA = 0 then b <- 0
- else b <-(RA)
- EA <- b + (RB)
-
-Special Registers Altered:
-
- None
-
-<!-- Section 5.9.3.3 TLB Management Instructions Page 1033 -->
-
-# TLB Invalidate Entry
-
-X-Form
-
-* tlbie RB,RS,RIC,PRS,R
-
-Pseudo-code:
-
- IS <- (RB) [52:53]
-
-Special Registers Altered:
-
- None
-
-<!-- MISSING tlbiel page 1038 -->
-<!-- MISSING tlbsync page 1042 -->
+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- Section 3.3.7 Fixed-Point Move Assist Instructions [Phased Out] pages 63 - 65 -->
-
-<!-- The Move Assist instructions allow movement of an arbitrary sequence of bytes -->
-<!-- from storage to registers or from registers to storage without concern for -->
-<!-- alignment. These instructions can be used for a short move between arbitrary -->
-<!-- storage locations or to initiate a long move between unaligned storage fields. -->
-
-
-# Load String Word Immediate
-
-X-Form
-
-* lswi RT,RA,NB
-
-Pseudo-code:
-
- EA <- (RA|0)
- if NB = 0 then n <- 32
- else n <- NB
- r <- RT - 1
- i <- 32
- do while n > 0
- if i = 32 then
- r <- (r + 1) % 32
- GPR(r) <- 0
- GPR(r)[i:i+7] <- MEM(EA, 1)
- i <- i + 8
- if i = 64 then i <- 32
- EA <- EA + 1
- n <- n - 1
-
-Special Registers Altered:
-
- None
-
-# Load String Word Indexed
-
-X-Form
-
-* lswx RT,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- n <- XER[57:63]
- r <- RT - 1
- i <- 32
- RT <- undefined([0]*64)
- do while n > 0
- if i = 32 then
- r <- (r + 1) % 32
- GPR(r) <- 0
- GPR(r)[i:i+7] <- MEM(EA, 1)
- i <- i + 8
- if i = 64 then i <- 32
- EA <- EA + 1
- n <- n - 1
-
-Special Registers Altered:
-
- None
-
-# Store String Word Immediate
-
-X-Form
-
-* stswi RS,RA,NB
-
-Pseudo-code:
-
- EA <- (RA|0)
- if NB = 0 then n <- 32
- else n <- NB
- r <- RS - 1
- i <- 32
- do while n > 0
- if i = 32 then r <- (r + 1) % 32
- MEM(EA, 1) <- GPR(r)[i:i+7]
- i <- i + 8
- if i = 64 then i <- 32
- EA <- EA + 1
- n <- n - 1
-
-Special Registers Altered:
-
- None
-
-# Store String Word Indexed
-
-X-Form
-
-* stswx RS,RA,RB
-
-Pseudo-code:
-
- b <- (RA|0)
- EA <- b + (RB)
- n <- XER[57:63]
- r <- RS - 1
- i <- 32
- do while n > 0
- if i = 32 then r <- (r + 1) % 32
- MEM(EA, 1) <- GPR(r)[i:i+7]
- i <- i + 8
- if i = 64 then i <- 32
- EA <- EA + 1
- n <- n - 1
-
-Special Registers Altered:
-
- None
-
-<!-- Checked March 2021 -->
+++ /dev/null
-<!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
-
-<!-- 3.3.1 System Linkage Instructions Page 952 - 956 -->
-
-<!-- These instructions provide the means by which a program can call upon the system to perform a service. -->
-
-# System Call
-
-SC-Form
-
-* sc LEV
-
-Pseudo-code:
-
- SRR0 <-iea CIA + 4
- SRR1[33:36] <- 0
- SRR1[42:47] <- 0
- SRR1[0:32] <- MSR[0:32]
- SRR1[37:41] <- MSR[37:41]
- SRR1[48:63] <- MSR[48:63]
- MSR <- new_value
- NIA <- 0x0000_0000_0000_0C00
-
-Special Registers Altered:
-
- SRR0 SRR1 MSR
-
-# System Call Vectored
-
-SC-Form
-
-* scv LEV
-
-Pseudo-code:
-
- LR <- CIA + 4
- SRR1[33:36] <- undefined([0]*4)
- SRR1[42:47] <- undefined([0]*6)
- SRR1[0:32] <- MSR[0:32]
- SRR1[37:41] <- MSR[37:41]
- SRR1[48:63] <- MSR[48:63]
- MSR <- new_value
- NIA <- vectored
-
-Special Registers Altered:
-
- LR CTR MSR
-
-# Return From System Call Vectored
-
-XL-Form
-
-* rfscv
-
-Pseudo-code:
-
- if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then
- MSR[29:31] <- CTR[29:31]
- MSR[48] <- CTR[49]
- MSR[58] <- CTR[49]
- MSR[59] <- CTR[49]
- MSR[0:2] <- CTR[0:2]
- MSR[4:28] <- CTR[4:28]
- MSR[32] <- CTR[32]
- MSR[37:41] <- CTR[37:41]
- MSR[49:50] <- CTR[49:50]
- MSR[52:57] <- CTR[52:57]
- MSR[60:63] <- CTR[60:63]
- NIA <-iea LR[0:61] || 0b00
-
-Special Registers Altered:
-
- MSR
-
-# Return From Interrupt Doubleword
-
-XL-Form
-
-* rfid
-
-Pseudo-code:
-
- MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51]))
- MSR[3] <- (MSR[3] & SRR1[3])
- if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
- MSR[29:31] <- SRR1[29:31]
- MSR[48] <- SRR1[48] | SRR1[49]
- MSR[58] <- SRR1[58] | SRR1[49]
- MSR[59] <- SRR1[59] | SRR1[49]
- MSR[0:2] <- SRR1[0:2]
- MSR[4:28] <- SRR1[4:28]
- MSR[32] <- SRR1[32]
- MSR[37:41] <- SRR1[37:41]
- MSR[49:50] <- SRR1[49:50]
- MSR[52:57] <- SRR1[52:57]
- MSR[60:63] <- SRR1[60:63]
- NIA <-iea SRR0[0:61] || 0b00
-
-Special Registers Altered:
-
- MSR
-
-# Hypervisor Return From Interrupt Doubleword
-
-XL-Form
-
-* hrfid
-
-Pseudo-code:
-
- if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then
- MSR[29:31] <- HSRR1[29:31]
- MSR[48] <- HSRR1[48] | HSRR1[49]
- MSR[58] <- HSRR1[58] | HSRR1[49]
- MSR[59] <- HSRR1[59] | HSRR1[49]
- MSR[0:28] <- HSRR1[0:28]
- MSR[32] <- HSRR1[32]
- MSR[37:41] <- HSRR1[37:41]
- MSR[49:57] <- HSRR1[49:57]
- MSR[60:63] <- HSRR1[60:63]
- NIA <-iea HSRR0[0:61] || 0b00
-
-Special Registers Altered:
-
- MSR
-
-<!-- Checked March 2021 -->
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-lwz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lbz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lhz,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lha,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-ld,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lwa,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-lwzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
-lbzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
-lhzu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
-lhau,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
-ldu,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-stw,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
-stb,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
-sth,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
-std,2P,EXTRA3,s:RS,s:RA,0,0,RA_OR_ZERO,0,RS,0,0,0,0
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-lwarx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-ldx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lwzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lbarx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-ldarx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lbzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lharx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lhzx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lwax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lhax,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-ldbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lwbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lwzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lhbrx,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lhzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-lbzcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-ldcix,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
-stwu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
-stbu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
-sthu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
-stdu,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
-ldux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lwzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lbzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lhzux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lwaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-lhaux,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
-stdux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
-stwux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
-stbux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
-sthux,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-stdx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stwx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stbx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-sthx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stdbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stwbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stwcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-sthbrx,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-sthcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stbcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stdcix,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0
-stwcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
-stdcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
-stbcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
-sthcx,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-crnor,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-crandc,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-crxor,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-crnand,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-crand,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-creqv,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-crorc,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-cror,1P,EXTRA3,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-cmp,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
-cmpl,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
-cmprb,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
-cmpeqb,1P,EXTRA3,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
-0/0=fcmpu,1P,EXTRA3,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
-1/0=fcmpo,1P,EXTRA3,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
-4/0=ftdiv,1P,EXTRA3,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
-bpermd,1P,EXTRA3,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0
-modud,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
-moduw,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
-cmpb,1P,EXTRA3,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0
-modsd,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
-modsw,1P,EXTRA3,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
-26/6=fmrgow,1P,EXTRA3,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
-30/6=fmrgew,1P,EXTRA3,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0
-rlwnm,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-rldcl,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-rldcr,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-subfc,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhdu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-addc,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhwu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-slw,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-sld,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-and,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-subf,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-andc,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-mulhd,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-nor,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-subfe,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-adde,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulld,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mullw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-add,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-eqv,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-xor,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-divdeu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divweu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-orc,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-divde,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divwe,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-or,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-divdu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divwu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-nand,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0
-divd,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-subfco,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhdu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-addco,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhwu,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-srw,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-srd,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-subfo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhd,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulhw,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-subfeo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-addeo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mulldo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-mullwo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-addo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-sraw,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-srad,1P,EXTRA3,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0
-divdeuo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divweuo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divdeo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divweo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divduo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divwuo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divdo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-divwo,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0
-fdivs,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-fsubs,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-fadds,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-fmuls,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0
-fdiv,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-fsub,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-fadd,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-fmul,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0
-0/8=fcpsgn,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0
-rlwimi,1P,EXTRA3,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
-rldimi,1P,EXTRA3,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
-rldimi,1P,EXTRA3,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-isel,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
-fmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
-fmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
-fnmsubs,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
-fnmadds,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-mcrf,2P,EXTRA3,d:BF,s:BFA,0,0,0,0,0,0,BFA,BF,0
-mfcr/mfocrf,2P,EXTRA3,d:RT,s:CR,0,0,0,0,0,RT,WHOLE_REG,0,0
-setb,2P,EXTRA3,d:RT,s:BFA,0,0,0,0,0,RT,BFA,0,0
-5/0=ftsqrt,2P,EXTRA3,d:BF,s:FRB,0,0,0,FRB,0,0,0,BF,0
-22/7=mtfsf,2P,EXTRA3,d:CR1,s:FRB,0,0,0,FRB,0,0,0,CR1,0
-cmpli,2P,EXTRA3,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0
-cmpi,2P,EXTRA3,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0
-neg,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
-popcntb,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-prtyw,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-prtyd,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-mfspr,2P,EXTRA3,d:RS,s:SPR,0,0,SPR,0,0,RT,0,0,0
-popcntw,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-mtspr,2P,EXTRA3,d:SPR,s:RS,0,0,RS,0,0,SPR,0,0,0
-popcntd,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-nego,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
-addic,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
-addi,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-addis,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-ori,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-oris,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-xori,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-xoris,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
-subfic,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
-cntlzw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-cntlzd,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-subfze,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-addze,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-cnttzw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-cnttzd,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-subfzeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-addzeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-extsh,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-extsb,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-extsw,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-fcfid[u]s,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fsqrts,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fres,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-frsqrtes,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fsqrt,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fre,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-frsqrte,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-18/7=mffsfamily,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-1/8=fneg,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-2/8=fmr,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-4/8=fnabs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-8/8=fabs,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-12/8=frin,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-13/8=friz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-14/8=frip,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-15/8=frim,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-0/12=frsp,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-0/14=fctiw,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-4/14=fctiwu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-25/14=fctid,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-26/14=fcfid,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-29/14=fctidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-30/14=fcfidu,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-0/15=fctiwz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-4/15=fctiwuz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-25/15=fctidz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-29/15=fctiduz,2P,EXTRA3,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-addic.,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-rlwinm,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-andi.,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-andis.,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
-mulli,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-rldicl,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-rldicl,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-rldicr,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-rldicr,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-rldic,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-rldic,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-subfme,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-addme,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-subfmeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-addmeo,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
-srawi,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-sradi,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-sradi,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-extswsli,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
-extswsli,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0
+++ /dev/null
-insn,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-mtcrf/mtocrf,2P,EXTRA2,d:CR,s:RS,s:CR,0,RS,0,0,0,WHOLE_REG,WHOLE_REG,0
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-000000---------------0100000000-,NONE,OP_ATTN,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,attn,NONE
-01100000000000000000000000000000,NONE,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,nop,D
-000001---------------0000000011-,NONE,OP_SIM_CONFIG,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sim_cfg,NONE
+++ /dev/null
-#1.6.1 I-FORM
- |0 |6 |30|31 |
- | PO | LI |AA|LK |
-
-#1.6.2 B-FORM
- |0 |6 |11 |16 |30|31 |
- | PO | BO| BI | BD |AA|LK |
-
-#1.6.3 SC-FORM
- |0 |6 |11 |16 |20 |27 |30 |31 |
- | PO | ///| ///| // | LEV | //| 1| / |
-
-#1.6.4 D-FORM
- |0 |6 |9 |10 |11 |16 |31 |
- | PO | RT | RA| D |
- | PO | RT | RA| SI |
- | PO | RS | RA| D |
- | PO | RS | RA| UI |
- | PO | BF | / | L | RA| SI |
- | PO | BF | / | L | RA| UI |
- | PO | TO | RA| SI |
- | PO | FRT | RA| D |
- | PO | FRS | RA| D |
-
-#1.6.5 DS-FORM
- |0 |6 |11 |16 |30 |31 |
- | PO | RT | RA | DS | XO |
- | PO | RS | RA | DS | XO |
- | PO | RSp | RA | DS | XO |
- | PO | FRTp | RA | DS | XO |
- | PO | FRSp | RA | DS | XO |
-
-#1.6.6 DQ-FORM
- |0 |6 |11 |16 |28|29 |31 |
- | PO | RTp | RA | DQ | PT |
- | PO | S | RA | DQ |SX| XO |
- | PO | T | RA | DQ |TX| XO |
-
-# 1.6.7 X-FORM
- |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
- | PO | RT | RA | /// | XO | / |
- | PO | RT | RA | RB | XO | / |
- | PO | RT | RA | RB | XO |EH |
- | PO | RT | RA | NB | XO | / |
- | PO | RT | /|SR | /// | XO | / |
- | PO | RT | /// | RB | XO | / |
- | PO | RT | /// | RB | XO | 1 |
- | PO | RT | /// | /// | XO | / |
- | PO | RS | RA | RB | XO |Rc |
- | PO | RT | RA | RB | XO |Rc |
- | PO | RS | RA | RB | XO | 1 |
- | PO | RS | RA | RB | XO | / |
- | PO | RS | RA | NB | XO | / |
- | PO | RS | RA | SH | XO |Rc |
- | PO | RS | RA | /// | XO |Rc |
- | PO | RS | RA | /// | XO | / |
- | PO | RS | /|SR | /// | XO | / |
- | PO | RS | /// | RB | XO | / |
- | PO | RS | /// | /// | XO | / |
- | PO | RS | /// |L1| /// | XO | / |
- | PO | TH | RA | RB | XO | / |
- | PO | BF |/ | L | RA | RB | XO | / |
- | PO | BF |// | FRA | FRB | XO | / |
- | PO | BF |// | BFA | // | /// | XO | / |
- | PO | BF |// | /// |W | U |/ | XO |Rc |
- | PO | BF |// | /// | /// | XO | / |
- | PO | TH | RA | RB | XO | / |
- | PO | /| CT | /// | /// | XO | / |
- | PO | /| CT | RA | RB | XO | / |
- | PO | /// | L2 | RA | RB | XO | / |
- | PO | /// | L2 | /// | RB | XO | / |
- | PO | /// | L2 | /// | /// | XO | / |
- | PO | /// | L2 | /| E | /// | XO | / |
- | PO | TO | RA | RB | XO | / |
- | PO | FRT | RA | RB | XO | / |
- | PO | FRT | FRA | FRB | XO | / |
- | PO | FRTp | RA | RB | XO | / |
- | PO | FRT | /// | FRB | XO |Rc |
- | PO | FRT | /// | FRBp | XO |Rc |
- | PO | FRT | /// | /// | XO |Rc |
- | PO | FRTp | /// | FRB | XO |Rc |
- | PO | FRTp | /// | FRBp | XO |Rc |
- | PO | FRTp | FRA | FRBp | XO |Rc |
- | PO | FRTp | FRAp | FRBp | XO |Rc |
- | PO | BF |// | FRA | FRBp | XO | / |
- | PO | BF |// | FRAp | FRBp | XO | / |
- | PO | FRT |S | | FRB | XO |Rc |
- | PO | FRTp |S | | FRBp | XO |Rc |
- | PO | FRS | RA | RB | XO | / |
- | PO | FRSp | RA | RB | XO | / |
- | PO | BT | /// | /// | XO |Rc |
- | PO | /// | RA | RB | XO | / |
- | PO | /// | /// | RB | XO | / |
- | PO | /// | /// | /// | XO | / |
- | PO | /// | /// | E|/// | XO | / |
- | PO | //|IH | /// | /// | XO | / |
- | PO | A|// | /// | /// | XO | 1 |
- | PO | A|// |R | /// | /// | XO | 1 |
- | PO | /// | RA | RB | XO | 1 |
- | PO | /// |WC | /// | /// | XO | / |
- | PO | /// |T | RA | RB | XO | / |
- | PO | VRT | RA | RB | XO | / |
- | PO | VRS | RA | RB | XO | / |
- | PO | MO | /// | /// | XO | / |
- | PO | RT | /// |L3 | /// | XO | / |
-
-# 1.6.8 XL-FORM
- |0 |6 |9 |11 |14 |16 |19|20|21 |31 |
- | PO | BT | BA | BB | XO | / |
- | PO | BO | BI | /// |BH | XO |LK |
- | PO | | /// |S | XO | / |
- | PO | BF |// |BFA |// | /// | XO | / |
- | PO | /// | XO | / |
- | PO | OC | XO | / |
-
-# 1.6.9 XFX-FORM
- |0 |6 |11|12 |20|21 |31 |
- | PO | RT | spr | XO | / |
- | PO | RT | tbr | XO | / |
- | PO | RT |0 | /// | XO | / |
- | PO | RT |1 | FXM |/ | XO | / |
- | PO | RT | dcr | XO | / |
- | PO | RT | pmrn | XO | / |
- | PO | RT | BHRBE | XO | / |
- | PO | DUI | DUIS | XO | / |
- | PO | RS |0 | FXM |/ | XO | / |
- | PO | RS |1 | FXM |/ | XO | / |
- | PO | RS | spr | XO | / |
- | PO | RS | dcr | XO | / |
- | PO | RS | pmrn | XO | / |
-
-# 1.6.10 XFL-FORM
- |0 |6|7 |15|16 |21 |31 |
- | PO |L| FLM |W |FRB | XO |Rc |
-
-# 1.6.11 XX1-FORM
- |0 |6 |11 |16 |21 |31 |
- | PO | T | RA | RB | XO |TX |
- | PO | S | RA | RB | XO |SX |
-
-# 1.6.12 XX2-FORM
- |0 |6 |9 |11 |14 |16 |21 |30|31 |
- | PO | T | /// | B |XO |BX|TX |
- | PO | T | /// |UIM | B |XO |BX|TX |
- | PO | BF | //| /// | B |XO |BX| / |
-
-# 1.6.13 XX3-FORM
- |0 |6 |9 |11 |16 |21 |22 |24 |29|30|31 |
- | PO | T | A | B | XO |AX|BX|TX |
- | PO | T | A | B |Rc | XO |AX|BX|TX |
- | PO | BF | // | A | B | XO |AX|BX|/ |
- | PO | T | A | B |XO |SHW | XO |AX|BX|TX |
- | PO | T | A | B |XO |DM | XO |AX|BX|TX |
-
-# 1.6.14 XX4-FORM
- |0 |6 |11 |16 |21 |26 |28|29 |30|31 |
- | PO | T | A | B | C | XO |CX|AX |BX|TX |
-
-# 1.6.15 XS-FORM
- |0 |6 |11 |16 |21 |30|31 |
- | PO | RS | RA | sh | XO |sh|Rc |
-
-# 1.6.16 XO-FORM
- |0 |6 |11 |16 |21 |22 |31 |
- | PO | RT| RA| RB |OE | XO |Rc |
- | PO | RT| RA| RB | /| XO |Rc |
- | PO | RT| RA| RB | /| XO | / |
- | PO | RT| RA| /// |OE | XO |Rc |
-
-# 1.6.17 A-FORM
- |0 |6 |11 |16 |21 |26 |31 |
- | PO | FRT | FRA | FRB | FRC | XO |Rc |
- | PO | FRT | FRA | FRB | /// | XO |Rc |
- | PO | FRT | FRA | /// | FRC | XO |Rc |
- | PO | FRT | /// | FRB | /// | XO |Rc |
- | PO | RT | RA | RB | BC | XO | /|
-
-# 1.6.18 M-FORM
- |0 |6 |11 |16 |21 |26 |31|
- | PO | RS | RA | RB | MB | ME |Rc|
- | PO | RS | RA | SH | MB | ME |Rc|
-
-# 1.6.19 MD-FORM
- |0 |6 |11 |16 |21 |27|30|31|
- | PO | RS | RA | sh | mb |XO|sh|Rc|
- | PO | RS | RA | sh | me |XO|sh|Rc|
-
-# 1.6.20 MDS-FORM
- |0 |6 |11 |16 |21 |27 |31|
- | PO | RS | RA | RB | mb | XO |Rc|
- | PO | RS | RA | RB | me | XO |Rc|
-
-# 1.6.21 VA-FORM
- |0 |6 |11 |16 |21|22 |26 |31|
- | PO | RT | RA | RB | RC | XO |
- | PO | VRT | VRA | VRB | VRC | XO |
- | PO | VRT | VRA | VRB | /|SHB| XO |
-
-# 1.6.22 VC-FORM
- |0 |6 |11 |16 |21|22 |31|
- | PO | VRT | VRA | VRB |Rc| XO |
-
-# 1.6.23 VX-FORM
- |0 |6 |11 |16 |21 |31|
- | PO | VRT | VRA | VRB | XO |
- | PO | VRT | /// | VRB | XO |
- | PO | VRT | UIM | VRB | XO |
- | PO | VRT | / UIM | VRB | XO |
- | PO | VRT | // UIM | VRB | XO |
- | PO | VRT | /// UIM | VRB | XO |
- | PO | VRT | SIM | ///| XO |
- | PO | VRT | ///| | XO |
- | PO | |/// | VRB | XO |
-
-# 1.6.24 EVX-FORM
- |0 |6 |9 |11 |16 |21 |31|
- | PO | RS | RA | RB | XO |
- | PO | RS | RA | UI | XO |
- | PO | RT | ///| RB | XO |
- | PO | RT | RA | RB | XO |
- | PO | RT | RA | ///| XO |
- | PO | RT | UI | RB | XO |
- | PO | BF|//| RA | RB | XO |
- | PO | RT | RA | UI | XO |
- | PO | RT | SI | ///| XO |
-
-# 1.6.25 EVS-FORM
- |0 |6 |11 |16 |21 |29 |31 |
- | PO | RT| RA | RB | XO |BFA |
-
-# 1.6.26 Z22-FORM
- |0 |6 |9 |11 |16 |22 |31 |
- | PO | BF|//| FRA | DCM | XO | / |
- | PO | BF|//| FRAp | DCM | XO | / |
- | PO | BF|//| FRA | DGM | XO | / |
- | PO | BF|//| FRAp | DGM | XO | / |
- | PO | FRT | FRA | SH | XO |Rc |
- | PO | FRTp| FRAp | SH | XO |Rc |
-
-# 1.6.27 Z23-FORM
- |0 |6 |11 |15 |16 |21 |23 |31 |
- | PO | FRT | TE | FRB |RMC| XO |Rc |
- | PO | FRTp| TE | FRBp |RMC| XO |Rc |
- | PO | FRT | FRA | FRB |RMC| XO |Rc |
- | PO | FRTp| FRA | FRBp |RMC| XO |Rc |
- | PO | FRTp| FRAp | FRBp |RMC| XO |Rc |
- | PO | FRT | /// | R | FRB |RMC| XO |Rc |
- | PO | FRTp| /// | R | FRBp |RMC| XO |Rc |
-
-# V3.0B 1.6.6 DX-FORM
- |0 |6 |11 |16 |26 |31
- | PO | RT| d1| d0| XO|d2
-
-# 1.6.28 SVL-FORM
- |0 |6 |11 |16 |22 |24 |25 |26 |31 |
- | PO | RT | RA | SVi |// |vs |ms | XO |Rc |
-
-# 1.6.28 Instruction Fields
- A (6)
- Field used by the tbegin. instruction to specify an
- implementation-specific function.
- Field used by the tend. instruction to specify the
- completion of the outer transaction and all nested
- transactions.
- Formats: X
- AA (30)
- Absolute Address.
- 0 The immediate field represents an address
- relative to the current instruction address. For
- I-form branches the effective address of the
- branch target is the sum of the LI field
- sign-extended to 64 bits and the address of
- the branch instruction. For B-form branches
- the effective address of the branch target is
- the sum of the BD field sign-extended to 64
- bits and the address of the branch instruction.
- 1 The immediate field represents an absolute
- address. For I-form branches the effective
- address of the branch target is the LI field
- sign-extended to 64 bits. For B-form branches
- the effective address of the branch target is
- the BD field sign-extended to 64 bits.
- Formats: B, I
- AX,A (29,11:15)
- Fields that are concatenated to specify a VSR to
- be used as a source.
- Formats: XX3, XX4
- BA (11:15)
- Field used to specify a bit in the CR to be used as
- a source.
- Formats: XL
- BB (16:20)
- Field used to specify a bit in the CR to be used as
- a source.
- Formats: XL
- BC (21:25)
- Field used to specify a bit in the CR to be used as
- a source.
- Formats: A
- BD (16:29)
- Immediate field used to specify a 14-bit signed
- two's complement branch displacement which is
- concatenated on the right with 0b00 and
- sign-extended to 64 bits.
- Formats: B
- BF (6:8)
- Field used to specify one of the CR fields or one of
- the FPSCR fields to be used as a target.
- Formats: D, X, XL, XX2, XX3, Z22
- BFA (29:31)
- Field used to specify one of the CR fields or one of
- the FPSCR fields to be used as a source.
- Formats: EVS
- BFA (11:13)
- Field used to specify one of the CR fields or one of
- the FPSCR fields to be used as a source.
- Formats: X, XL
- BH (19:20)
- Field used to specify a hint in the Branch Condi-
- tional to Link Register and Branch Conditional to
- Count Register instructions. The encoding is
- described in Section 2.4, 'Branch Instructions'.
- Formats: XL
- BHRBE (11:20)
- Field used to identify the BHRB entry to be used
- as a source by the Move From Branch History
- Rolling Buffer instruction.
- Formats: XFX
- BI (11:15)
- Field used to specify a bit in the CR to be tested by
- a Branch Conditional instruction.
- Formats: B, XL
- BO (6:10)
- Field used to specify options for the Branch Condi-
- tional instructions. The encoding is described in
- Section 2.4, 'Branch Instructions'.
- Formats: B, XL, X, XL
- BT (6:10)
- Field used to specify a bit in the CR or in the
- FPSCR to be used as a target.
- Formats: XL
- BX,B (30,16:20)
- Fields that are concatenated to specify a VSR to
- be used as a source.
- Formats: XX2, XX3, XX4
- CT (7:10)
- Field used in X-form instructions to specify a cache
- target (see Section 4.3.2 of Book II).
- Formats: X
- CX,C (28,21:25)
- Fields that are concatenated to specify a VSR to
- be used as a source.
- Formats: XX4
- D (16:31)
- Immediate field used to specify a 16-bit signed
- two's complement integer which is sign-extended
- to 64 bits.
- Formats: D
- d0,d1,d2 (16:25,11:15,31)
- Immediate fields that are concatenated to specify a
- 16-bit signed two's complement integer which is
- sign-extended to 64 bits.
- Formats: DX
- dc,dm,dx (25,29,11:15)
- Immediate fields that are concatenated to specify
- Data Class Mask.
- Formats: XX2
- DCM (16:21)
- Immediate field used to specify Data Class Mask.
- Formats: Z22
- DCMX (9:15)
- Immediate field used to specify Data Class Mask.
- Formats: X, XX2
- DGM (16:21)
- Immediate field used as the Data Group Mask.
- Formats: Z22
- DM (22:23)
- Immediate field used by xxpermdi instruction as
- doubleword permute control.
- Formats: XX3
- DRM (18:20)
- Immediate operand field used to specify new deci-
- mal floating-point rounding mode.
- Formats: X
- DUI (6:10)
- Field used by the dnh instruction (see Book III-E).
- Formats: XFX
- DUIS (11:20)
- Field used by the dnh instruction (see Book III-E).
- Formats: XFX
- DQ (16:27)
- Immediate field used to specify a 12-bit signed
- two's complement integer which is concatenated
- on the right with 0b0000 and sign-extended to 64
- bits.
- Formats: DQ
- DS (16:29)
- Immediate field used to specify a 14-bit signed
- two's complement integer which is concatenated
- on the right with 0b00 and sign-extended to 64 bits.
- Formats: DS
- E (16)
- Field used by the Write MSR External Enable
- instruction (see Book III-E).
- Formats: X
- E (12:15)
- Field used to specify the access types ordered by
- an Elemental Memory Barrier type of sync instruc-
- tion.
- EH (31)
- Field used to specify a hint in the Load and
- Reserve instructions. The meaning is described in
- Section 4.6.2, 'Load and Reserve and Store Con-
- ditional Instructions', in Book II.
- Formats: X
- EO (11:12)
- Expanded opcode field
- Formats: X
- EO (11:15)
- Expanded opcode field
- Formats: VX, X, XX2
- EX (31)
- Field used to specify Inexact form of round to
- quad-precision integer.
- Formats: X
- FC (16:20)
- Field used to specify the function code in Load/
- Store Atomic instructions.
- Formats: X
- FLM (7:14)
- Field mask used to identify the FPSCR fields that
- are to be updated by the mtfsf instruction.
- Formats: XFL
- FRA (11:15)
- Field used to specify a FPR to be used as a
- source.
- Formats: A, X, Z22, Z23
- FRAp (11:15)
- Field used to specify an even/odd pair of FPRs to
- be concatenated and used as a source.
- Formats: X, Z22, Z23
- FRB (16:20)
- Field used to specify an FPR to be used as a
- source.
- Formats: A, X, XFL, Z23
- FRBp (16:20)
- Field used to specify an even/odd pair of FPRs to
- be concatenated and used as a source.
- Formats: X, Z23
- FRC (21:25)
- Field used to specify an FPR to be used as a
- source.
- Formats: A
- FRS (6:10)
- Field used to specify an FPR to be used as a
- source.
- Formats: D, X
- FRSp (6:10)
- Field used to specify an even/odd pair of FPRs to
- be concatenated and used as a source.
- Formats: DS, X
- FRT (6:10)
- Field used to specify an FPR to be used as a tar-
- get.
- Formats: A, D, X, Z22, Z23
- FRTp (6:10)
- Field used to specify an even/odd pair of FPRs to
- be concatenated and used as a target.
- Formats: DS, X, Z22, Z23
- FXM (12:19)
- Field mask used to identify the CR fields that are to
- be written by the mtcrf and mtocrf instructions, or
- read by the mfocrf instruction.
- Formats: XFX
- IB (16:20)
- Immediate field used to specify a 5-bit signed inte-
- ger.
- Formats: MDS
- IH (8:10)
- Field used to specify a hint in the SLB Invalidate
- All instruction. The meaning is described in
- Section 5.9.3.2, 'SLB Management Instructions',
- in Book III.
- Formats: X
- IMM8 (13:20)
- Immediate field used to specify an 8-bit integer.
- Formats: X
- IS (6:10)
- Immediate field used to specify a 5-bit signed inte-
- ger.
- Formats: MDS
- L (6)
- Field used to specify whether the mtfsf instruction
- updates the entire FPSCR.
- Formats: XFL
- L2 (9:10)
- Field used by the Data Cache Block Flush instruc-
- tion (see Section 4.3.2 of Book II) and also by the
- Synchronize instruction (see Section 4.6.3 of Book
- II).
- Formats: X
- L (10)
- Field used to specify whether a fixed-point Com-
- pare instruction is to compare 64-bit numbers or
- 32-bit numbers.
- Field used by the Compare Range Byte instruction
- to indicate whether to compare against 1 or 2
- ranges of bytes.
- Formats: D, X
- L1 (15)
- Field used by the Move To Machine State Register
- instruction (see Book III).
- Field used by the SLB Move From Entry VSID and
- SLB Move From Entry ESID instructions for imple-
- mentation-specific purposes.
- Formats: X
- L3 (14:15)
- Field used by the Deliver A Random Number
- instruction (see Section 3.3.9, 'Fixed-Point Arith-
- metic Instructions') to choose the random number
- format.
- Formats: X
- LEV (20:26)
- Field used by the System Call instructions.
- Formats: SC
- LI (6:29)
- Immediate field used to specify a 24-bit signed
- two's complement integer which is concatenated
- on the right with 0b00 and sign-extended to 64
- bits.
- Formats: I
- LK (31)
- LINK bit.
- 0 Do not set the Link Register.
- 1 Set the Link Register. The address of the
- instruction following the Branch instruction is
- placed into the Link Register.
- Formats: B, I, XL
- MB (21:25)
- Field used in M-form instructions to specify the first
- 1-bit of a 64-bit mask, as described in
- Section 3.3.14, 'Fixed-Point Rotate and Shift
- Instructions' on page 101.
- Formats: M
- mb (21:26)
- Field used in MD-form and MDS-form instructions
- to specify the first 1-bit of a 64-bit mask, as
- described in Section 3.3.14, 'Fixed-Point Rotate
- and Shift Instructions' on page 101.
- Formats: MD, MDS
- me (21:26)
- Field used in MD-form and MDS-form instructions
- to specify the last 1-bit of a 64-bit mask, as
- described in Section 3.3.14, 'Fixed-Point Rotate
- and Shift Instructions' on page 101.
- Formats: MD, MDS
- ME (26:30)
- Field used in M-form instructions to specify the last
- 1-bit of a 64-bit mask, as described in
- Section 3.3.14, 'Fixed-Point Rotate and Shift
- Instructions' on page 101.
- Formats: M
- MO (6:10)
- Field used in X-form instructions to specify a sub-
- set of storage accesses.
- Formats: X
- ms (25)
- Field used in Simple-V to specify whether MVL is to be set
- Formats: SVL
- NB (16:20)
- Field used to specify the number of bytes to move
- in an immediate Move Assist instruction.
- Formats: X
- OC (6:20)
- Field used by the Embedded Hypervisor Privilege
- instruction.
- Formats: XL
- OE (21)
- Field used by XO-form instructions to enable set-
- ting OV and SO in the XER.
- Formats: XO
- PO (0:5)
- Primary opcode field.
- Formats: all
- PRS (14)
- Field used to specify whether to invalidate pro-
- cess- or partition-scoped entries for tlbie[l].
- Formats: X
- PS (22)
- Field used to specify preferred sign for BCD opera-
- tions.
- Formats: VX
- PT (28:31)
- Immediate field used to specify a 4-bit unsigned
- value.
- Formats: DQ
- R (10)
- Field used by the tbegin. instruction to specify the
- start of a ROT.
- Formats: X
- R (15)
- Immediate field that specifies whether the RMC is
- specifying the primary or secondary encoding
- Field used to specify whether to invalidate Radix
- Tree or HPT entries for tlbie[l].
- Formats: X, Z23
- RA (11:15)
- Field used to specify a GPR to be used as a
- source or as a target.
- Formats: A, D, DQ, DQE, DS, M, MD, MDS, TX, VA, VX, X, XO, XS, SVL
- RB (16:20)
- Field used to specify a GPR to be used as a
- source.
- Formats: A, M, MDS, VA, X, XO
- Rc (21)
- RECORD bit.
- 0 Do not alter the Condition Register.
- 1 Set Condition Register Field 6 as described in
- Section 2.3.1, 'Condition Register' on
- page 30.
- Formats: VC, XX3
- RC (21:25)
- Field used to specify a GPR to be used as a
- source.
- Formats: VA
- Rc (31)
- RECORD bit.
- 0 Do not alter the Condition Register.
- 1 Set Condition Register Field 0 or Field 1 as
- described in Section 2.3.1, 'Condition Regis-
- ter' on page 30.
- Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL
- RIC (12:13)
- Field used to specify what types of entries to inval-
- idate for tlbie[l].
- Formats: X
- RM (19:20)
- Immediate operand field used to specify new
- binary floating-point rounding mode.
- Formats: X
- RMC (21:22)
- Immediate field used for DFP rounding mode con-
- trol.
- Formats: Z23
- RO (31)
- Round to Odd override
- Formats: X
- RS (6:10)
- Field used to specify a GPR to be used as a
- source.
- Formats: D, DS, M, MD, MDS, X, XFX, XS
- RSp (6:10)
- Field used to specify an even/odd pair of GPRs to
- be concatenated and used as a source.
- Formats: DS, X
- RT (6:10)
- Field used to specify a GPR to be used as a target.
- Formats: A, D, DQE, DS, DX, VA, VX, X, XFX, XO, XX2, SVL
- RTp (6:10)
- Field used to specify an even/odd pair of GPRs to
- be concatenated and used as a target.
- Formats: DQ, X
- S (11)
- Immediate field that specifies signed versus
- unsigned conversion.
- Formats: X
- S (20)
- Immediate field that specifies whether or not the
- rfebb instruction re-enables event-based
- branches.
- Formats: XL
- SH (16:20)
- Field used to specify a shift amount.
- Formats: M, X
- SH (16:21)
- Field used to specify a shift amount.
- Formats: Z22
- sh (30,16:20)
- Fields that are concatenated to specify a shift
- amount.
- Formats: MD, XS
- SHB (22:25)
- Field used to specify a shift amount in bytes.
- Formats: VA
- SHW (22:23)
- Field used to specify a shift amount in words.
- Formats: XX3
- SI (16:20)
- Immediate field used to specify a 5-bit signed inte-
- ger.
- Formats: X
- SI (16:31)
- Immediate field used to specify a 16-bit signed
- integer.
- Formats: D
- SIM (11:15)
- Immediate field used to specify a 5-bit signed inte-
- ger.
- Formats: VX
- SP (11:12)
- Immediate field that specifies signed versus
- unsigned conversion.
- Formats: X
- SPR (11:20)
- Field used to specify a Special Purpose Register
- for the mtspr and mfspr instructions.
- Formats: XFX
- SR (12:15)
- Field used by the Segment Register Manipulation
- instructions (see Book III).
- Formats: X
- SVi (16:23)
- Simple-V immediate field for setting VL or MVL
- Formats: SVL
- SX,S (28,6:10)
- Fields SX and S are concatenated to specify a
- VSR to be used as a source.
- Formats: DQ
- SX,S (31,6:10)
- Fields SX and S are concatenated to specify a
- VSR to be used as a source.
- Formats: X
- T (9:10)
- Field used to specify the type of invalidation done
- by a TLB Invalidate Local instruction (see Book
- III-E).
- Formats: X
- TBR (11:20)
- Field used by the Move From Time Base instruc-
- tion (see Section 6.1 of Book II).
- Formats: X
- TE (11:15)
- Immediate field that specifies a DFP exponent.
- Formats: Z23
- TH (6:10)
- Field used by the data stream variant of the dcbt
- and dcbtst instructions (see Section 4.3.2 of Book
- II).
- Formats: X
- TO (6:10)
- Field used to specify the conditions on which to
- trap. The encoding is described in
- Section 3.3.10.1, 'Character-Type Compare
- Instructions' on page 87.
- Formats: D, X
- TX,T (28,6:10)
- Fields that are concatenated to specify a VSR to
- be used as either a target.
- Formats: DQ
- TX,T (31,6:10)
- Fields that are concatenated to specify a VSR to
- be used as either a target or a source.
- Formats: X, XX2, XX3, XX4
- U (16:19)
- Immediate field used as the data to be placed into
- a field in the FPSCR.
- Formats: X
- UI (16:20)
- Immediate field used to specify a 5-bit unsigned
- integer.
- Formats: TX
- UI (16:31)
- Immediate field used to specify a 16-bit unsigned
- integer.
- Formats: D
- UIM (11:15)
- Immediate field used to specify a 5-bit unsigned
- integer.
- Formats: VX, X
- UIM (12:15)
- Immediate field used to specify a 4-bit unsigned
- integer.
- Formats: VX, XX2
- UIM (13:15)
- Immediate field used to specify a 3-bit unsigned
- integer.
- Formats: VX
- UIM (14:15)
- Immediate field used to specify a 2-bit unsigned
- integer.
- Formats: VX, XX2
- VRA (11:15)
- Field used to specify a VR to be used as a source.
- Formats: VA, VC, VX
- VRB (16:20)
- Field used to specify a VR to be used as a source.
- Formats: VA, VC, VX
- VRC (21:25)
- Field used to specify a VR to be used as a source.
- Formats: VA
- VRS (6:10)
- Field used to specify a VR to be used as a source.
- Formats: DS, X
- VRT (6:10)
- Field used to specify a VR to be used as a target.
- Formats: DS, VA, VC, VX, X
- vs (24)
- Field used in Simple-V to specify whether VL is to be set
- Formats: SVL
- W (15)
- Field used by the mtfsfi and mtfsf instructions to
- specify the target word in the FPSCR.
- Formats: X, XFL
- WC (9:10)
- Field used to specify the condition or conditions
- that cause instruction execution to resume after
- executing a wait instruction (see Section 4.6.4 of
- Book II).
- Formats: X
- XBI (21:24)
- Field used to specify a bit in the XER.
- Formats: MDS, MDS, TX
- XO (21,23:31)
- Extended opcode field.
- Formats: VX
- XO (21:24,26:28)
- Extended opcode field.
- Formats: XX2
- XO (21:24:28)
- Extended opcode field.
- Formats: XX3
- XO (21:28)
- Extended opcode field.
- Formats: XX3
- XO (21:29)
- Extended opcode field.
- Formats: XS, XX2
- XO (21:30)
- Extended opcode field.
- Formats: X, XFL, XFX, XL
- XO (21:31)
- Extended opcode field.
- Formats: VX
- XO (22:30)
- Extended opcode field.
- Formats: XO, XX3, Z22
- XO (22:31)
- Extended opcode field.
- Formats: VC
- XO (23:30)
- Extended opcode field.
- Formats: X, Z23
- XO (25:30)
- Extended opcode field.
- Formats: TX
- XO (26:27)
- Extended opcode field.
- Formats: XX4
- XO (26:30)
- Extended opcode field.
- Formats: A, DX, SVL
- XO (26:31)
- Extended opcode field.
- Formats: VA
- XO (27:29)
- Extended opcode field.
- Formats: MD
- XO (27:30)
- Extended opcode field.
- Formats: MDS
- XO (29:31)
- Extended opcode field.
- Formats: DQ
- XO (30)
- Extended opcode field.
- Formats: SC
- XO (30:31)
- Extended opcode field.
- Formats: DQE, DS, SC
-
+++ /dev/null
-fields.text
\ No newline at end of file
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic,D
-13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.,D
-14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi,D
-15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addis,D
-17,TRAP,OP_SC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,sc,SC
-28,LOGICAL,OP_AND,RS,CONST_UI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andi.,B
-29,LOGICAL,OP_AND,RS,CONST_UI_HI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andis.,B
-18,BRANCH,OP_B,NONE,CONST_LI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,b,I
-16,BRANCH,OP_BC,SPR,CONST_BD,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc,B
-11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi,D
-10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli,D
-34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D
-35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D
-42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D
-43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D
-40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D
-41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D
-32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D
-33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D
-7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D
-24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D
-25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D
-20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M
-21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M
-23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M
-38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D
-39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D
-44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D
-45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,D
-36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,D
-37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu,D
-8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,1,0,ONE,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic,D
-2,TRAP,OP_TRAP,RA,CONST_SI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi,D
-3,TRAP,OP_TRAP,RA,CONST_SI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,1,twi,D
-26,LOGICAL,OP_XOR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xori,D
-27,LOGICAL,OP_XOR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris,D
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b0000000000,CR,OP_MCRF,NONE,NONE,NONE,NONE,BFA,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mcrf,XL
-0b0100000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crand,XL
-0b0010000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crandc,XL
-0b0100100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,creqv,XL
-0b0011100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crnand,XL
-0b0000100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crnor,XL
-0b0111000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cror,XL
-0b0110100001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crorc,XL
-0b0011000001,CR,OP_CROP,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crxor,XL
-0b1000010000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bcctr,XL
-0b0000010000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bclr,XL
-0b1000110000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bctar,XL
-0b0010010110,ALU,OP_ISYNC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isync,XL
-0b0000010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,rfid,XL
-0b0100010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,hrfid,XL
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b00010,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,add pcis not implemented yet,DX
+++ /dev/null
-opcode,valid,comment
------00010,1,addpcis: 5 upper bits are part of constant
-1000010000,1,bcctr
-0000010000,1,bclr
-1000110000,0,bctar
-0100000001,1,crand
-0010000001,1,crandc
-0100100001,1,creqv
-0011100001,1,crnand
-0000100001,1,crnor
-0111000001,1,cror
-0110100001,1,crorc
-0011000001,1,crxor
-0010010110,1,isync
-0000000000,1,mcrf
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b00000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b0100,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD
-0b0101,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldic,MD
-0b0000,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS
-0b0001,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicl,MDS
-0b0010,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD
-0b0011,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldicr,MD
-0b0110,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD
-0b0111,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldimi,MD
-0b1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcl,MD
-0b1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,rldcr,MD
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b0100001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,add,XO
-0b1100001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,addo,XO
-0b0000001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,RC,0,0,addc,XO
-0b1000001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,RC,0,0,addco,XO
-0b0010001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,adde,XO
-0b1010001010,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addeo,XO
-0b0011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addme,XO
-0b1011101010,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addmeo,XO
-0b0011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addze,XO
-0b1011001010,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,0,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,addzeo,XO
-0b0000011100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,and,X
-0b0000111100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,andc,X
-0b0011111100,LOGICAL,OP_BPERM,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bpermd,X
-0b0000000000,ALU,OP_CMP,RA,RB,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmp,X
-0b0111111100,LOGICAL,OP_CMPB,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpb,X
-0b0011100000,ALU,OP_CMPEQB,RA,RB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpeqb,X
-0b0000100000,ALU,OP_CMP,RA,RB,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpl,X
-0b0011000000,,,RA,RB,NONE,NONE,NONE,BF,,,,,,,,,,,,,,,cmprb,X
-0b0000111010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cntlzd,X
-0b0000011010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,cntlzw,X
-0b1000111010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cnttzd,X
-0b1000011010,LOGICAL,OP_CNTZ,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,cnttzw,X
-0b1011110011,,,,,RT,,,,,,,,,,,,,,,,,,darn,X
-0b0001010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbf,X
-0b0000110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbst,X
-0b0100010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbt,X
-0b0011110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,dcbtst,X
-0b1111110110,MMU,OP_DCBZ,RA_OR_ZERO,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,dcbz,X
-0b0110001001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divdeu,XO
-0b1110001001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divdeuo,XO
-0b0110001011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divweu,XO
-0b1110001011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divweuo,XO
-0b0110101001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divde,XO
-0b1110101001,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divdeo,XO
-0b0110101011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divwe,XO
-0b1110101011,DIV,OP_DIVE,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divweo,XO
-0b0111001001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divdu,XO
-0b1111001001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,divduo,XO
-0b0111001011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divwu,XO
-0b1111001011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,divwuo,XO
-0b0111101001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divd,XO
-0b1111101001,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,divdo,XO
-0b0111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divw,XO
-0b1111101011,DIV,OP_DIV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,divwo,XO
-0b0100011100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,eqv,X
-0b1110111010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,0,extsb,X
-0b1110011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,0,0,0,RC,0,0,extsh,X
-0b1111011010,ALU,OP_EXTS,RS,NONE,NONE,RA,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,0,0,0,RC,0,0,extsw,X
-0b1101111010,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS
-0b1101111011,SHIFT_ROT,OP_EXTSWSLI,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,extswsli,XS
-0b1111010110,ALU,OP_ICBI,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbi,X
-0b0000010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,icbt,X
-0b0000001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0000101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0001001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0001101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0010001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0010101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0011001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0011101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0100001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0100101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0101001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0101101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0110001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0110101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0111001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0111101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1000001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1000101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1001001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1001101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1010001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1010101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1011001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1011101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1100001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1100101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1101001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1101101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1110001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1110101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1111001111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b1111101111,CR,OP_ISEL,RA_OR_ZERO,RB,NONE,RT,BC,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isel,A
-0b0000110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,1,0,0,NONE,0,1,lbarx,X
-0b1101010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,cix,0,0,0,NONE,0,0,lbzcix,X
-0b0001110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzux,X
-0b0001010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbzx,X
-0b0001010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,1,0,0,NONE,0,1,ldarx,X
-0b1000010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,1,0,0,0,0,0,NONE,0,1,ldbrx,X
-0b1101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,0,ldcix,X
-0b0000110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldux,X
-0b0000010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ldx,X
-0b0001110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,1,0,0,NONE,0,1,lharx,X
-0b0101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhaux,X
-0b0101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lhax,X
-0b1100010110,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,1,0,0,0,0,0,NONE,0,1,lhbrx,X
-0b1100110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,0,lhzcix,X
-0b0100110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzux,X
-0b0100010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhzx,X
-0b0000010100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,1,0,0,NONE,0,1,lwarx,X
-0b0101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,1,0,0,0,NONE,0,1,lwaux,X
-0b0101010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwax,X
-0b1000010110,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,1,0,0,0,0,0,NONE,0,1,lwbrx,X
-0b1100010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,cix,0,0,0,NONE,0,0,lwzcix,X
-0b0000110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzux,X
-0b0000010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwzx,X
-0b1000000000,,,,,,,,,,,,,,,,,,,,,,,mcrxr,X
-0b1001000000,,,,,,,,,,,,,,,,,,,,,,,mcrxrx,X
-0b0000010011,CR,OP_MFCR,NONE,NONE,NONE,RT,WHOLE_REG,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfcr/mfocrf,XFX
-0b0001010011,TRAP,OP_MFMSR,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mfmsr,X
-0b0101010011,SPR,OP_MFSPR,SPR,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfspr,XFX
-0b0100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,modud,X
-0b0100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,moduw,X
-0b1100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,modsd,X
-0b1100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,1,NONE,0,0,modsw,X
-0b0010010000,CR,OP_MTCRF,RS,NONE,NONE,NONE,WHOLE_REG,WHOLE_REG,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtcrf/mtocrf,XFX
-0b0010110010,TRAP,OP_MTMSRD,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd,X
-0b0010010010,TRAP,OP_MTMSR,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsr,X
-0b0111010011,SPR,OP_MTSPR,RS,NONE,NONE,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
-0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
-0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO
-0b0001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO
-0b0000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,mulhwu,XO
-0b1001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
-0b1000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO
-0b1001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO
-0b1000001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,mulhwu,XO
-0b0011101001,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulld,XO
-0b1011101001,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulldo,XO
-0b0011101011,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mullw,XO
-0b1011101011,MUL,OP_MUL_L64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mullwo,XO
-0b0111011100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,nand,X
-0b0001101000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,NONE,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,neg,XO
-0b1001101000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,NONE,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,nego,XO
-0b0001111100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,nor,X
-0b0110111100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,or,X
-0b0110011100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,orc,X
-0b0001111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,0,popcntb,X
-0b0111111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,popcntd,X
-0b0101111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,popcntw,X
-0b0010111010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,prtyd,X
-0b0010011010,LOGICAL,OP_PRTY,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,prtyw,X
-0b0010000000,CR,OP_SETB,NONE,NONE,NONE,RT,BFA,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,setb,VX
-0b0111110010,MMU,OP_TLBIE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,slbia,X
-0b0000011011,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,sld,X
-0b0000011000,SHIFT_ROT,OP_SHL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,slw,X
-0b1100011010,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,srad,X
-0b1100111010,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS
-0b1100111011,SHIFT_ROT,OP_SHR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,1,RC,0,0,sradi,XS
-0b1100011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,sraw,X
-0b1100111000,SHIFT_ROT,OP_SHR,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,1,1,RC,0,0,srawi,X
-0b1000011011,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,srd,X
-0b1000011000,SHIFT_ROT,OP_SHR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,srw,X
-0b1111010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,cix,0,0,0,NONE,0,1,stbcix,X
-0b1010110110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is1B,0,0,0,1,0,0,ONE,0,1,stbcx,X
-0b0011110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbux,X
-0b0011010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stbx,X
-0b1010010100,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,1,0,0,0,0,0,NONE,0,1,stdbrx,X
-0b1111110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,1,stdcix,X
-0b0011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is8B,0,0,0,1,0,0,ONE,0,1,stdcx,X
-0b0010110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdux,X
-0b0010010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stdx,X
-0b1110010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,1,0,0,0,0,0,NONE,0,1,sthbrx,X
-0b1110110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,1,sthcix,X
-0b1011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,1,0,0,ONE,0,1,sthcx,X
-0b0110110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthux,X
-0b0110010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sthx,X
-0b1010010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,1,0,0,0,0,0,NONE,0,1,stwbrx,X
-0b1110010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,cix,0,0,0,NONE,0,1,stwcix,X
-0b0010010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,1,0,0,ONE,0,1,stwcx,X
-0b0010110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwux,X
-0b0010010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stwx,X
-0b0000101000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,subf,XO
-0b1000101000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,0,NONE,0,0,0,0,0,0,RC,0,0,subfo,XO
-0b0000001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,1,NONE,0,0,0,0,0,0,RC,0,0,subfc,XO
-0b1000001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,ONE,1,NONE,0,0,0,0,0,0,RC,0,0,subfco,XO
-0b0010001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfe,XO
-0b1010001000,ALU,OP_ADD,RA,RB,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfeo,XO
-0b0011101000,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfme,XO
-0b1011101000,ALU,OP_ADD,RA,CONST_M1,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfmeo,XO
-0b0011001000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfze,XO
-0b1011001000,ALU,OP_ADD,RA,NONE,NONE,RT,NONE,CR0,1,0,CA,1,NONE,0,0,0,0,0,0,RC,0,0,subfzeo,XO
-0b1001010110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sync,X
-0b0001000100,TRAP,OP_TRAP,RA,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,td,X
-0b0000000100,TRAP,OP_TRAP,RA,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,1,tw,X
-0b0100110010,MMU,OP_TLBIE,NONE,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,tlbie,X
-0b0100010010,MMU,OP_TLBIE,NONE,RB,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,tlbiel,X
-0b0100111100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,xor,X
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0,LDST,OP_LOAD,RA_OR_ZERO,CONST_DS,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ld,DS
-1,LDST,OP_LOAD,RA_OR_ZERO,CONST_DS,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldu,DS
-2,LDST,OP_LOAD,RA_OR_ZERO,CONST_DS,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwa,DS
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b01110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcfid[u]s,
-0b10010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fdivs,
-0b10100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsubs,
-0b10101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fadds,
-0b10110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsqrts,
-0b11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fres,
-0b11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmuls,
-0b11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,frsqrtes,
-0b11100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,
-0b11101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,
-0b11110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,
-0b11111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,0,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,std,DS
-1,LDST,OP_STORE,RA_OR_ZERO,CONST_DS,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdu,DS
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b0010,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fdiv,
-0b0100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsub,
-0b0101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fadd,
-0b0110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsqrt,
-0b0111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fsel,
-0b1000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fre,
-0b1001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmul,
-0b1010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,frsqrte,
-0b1100,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmsub,
-0b1101,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fmadd,
-0b1110,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fnmsub,
-0b1111,FPU,OP_FPOP,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fnmadd,
+++ /dev/null
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form
-0b000000000,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,0/0=fcmpu,
-0b000000001,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,1/0=fcmpo,
-0b000000010,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,2/0=mcrfs,
-0b000000100,FPU,OP_FPOP,FRA,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,4/0=ftdiv,
-0b000000101,FPU,OP_FPOP,NONE,FRB,NONE,NONE,NONE,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,5/0=ftsqrt,
-0b011000001,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,1/6=mtfsb1,
-0b011000010,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,2/6=mtfsb0,
-0b011000100,FPU,OP_FPOP,NONE,NONE,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/6=mtfsfi,
-0b011011010,FPU,OP_FPOP_I,FRA,FRB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,26/6=fmrgow,
-0b011011110,FPU,OP_FPOP_I,FRA,FRB,NONE,FRT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,30/6=fmrgew,
-0b011110010,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,18/7=mffsfamily,
-0b011110110,FPU,OP_FPOP_I,NONE,FRB,NONE,NONE,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,22/7=mtfsf,
-0b100000000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/8=fcpsgn,
-0b100000001,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,1/8=fneg,
-0b100000010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,2/8=fmr,
-0b100000100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/8=fnabs,
-0b100001000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,8/8=fabs,
-0b100001100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,12/8=frin,
-0b100001101,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,13/8=friz,
-0b100001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,14/8=frip,
-0b100001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,15/8=frim,
-0b110000000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,0/12=frsp,
-0b111000000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/14=fctiw,
-0b111000100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/14=fctiwu,
-0b111011001,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,25/14=fctid,
-0b111011010,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,26/14=fcfid,
-0b111011101,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,29/14=fctidu,
-0b111011110,FPU,OP_FPOP_I,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,30/14=fcfidu,
-0b111100000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,0/15=fctiwz,
-0b111100100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,4/15=fctiwuz,
-0b111111001,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,25/15=fctidz,
-0b111111101,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,29/15=fctiduz,
+++ /dev/null
-Idx,SPR,priv_mtspr,priv_mfspr,len
-1,XER,no,no,64
-3,DSCR,no,no,64
-8,LR,no,no,64
-9,CTR,no,no,64
-13,AMR,no,no,64
-17,DSCR_priv,yes,yes,64
-18,DSISR,yes,yes,32
-19,DAR,yes,yes,64
-22,DEC,yes,yes,64
-26,SRR0,yes,yes,64
-27,SRR1,yes,yes,64
-28,CFAR,yes,yes,64
-29,AMR_priv,yes,yes,64
-48,PIDR,yes,yes,32
-61,IAMR,yes,yes,64
-128,TFHAR,no,no,64
-129,TFIAR,no,no,64
-130,TEXASR,no,no,64
-131,TEXASRU,no,no,32
-136,CTRL,-,no,32
-144,TIDR,yes,yes,64
-152,CTRL_priv,yes,-,32
-153,FSCR,yes,yes,64
-157,UAMOR,yes,yes,64
-158,GSR,yes,-,0
-159,PSPB,yes,yes,32
-176,DPDES,hypv,yes,64
-180,DAWR0,hypv,hypv,64
-186,RPR,hypv,hypv,64
-187,CIABR,hypv,hypv,64
-188,DAWRX0,hypv,hypv,32
-190,HFSCR,hypv,hypv,64
-256,VRSAVE,no,no,32
-259,SPRG3,-,no,64
-268,TB,-,no,64
-269,TBU,-,no,32
-272,SPRG0_priv,yes,yes,64
-273,SPRG1_priv,yes,yes,64
-274,SPRG2_priv,yes,yes,64
-275,SPRG3_priv,yes,yes,64
-283,CIR,-,yes,32
-284,TBL,hypv,-,32
-285,TBU_hypv,hypv,-,32
-286,TBU40,hypv,-,64
-287,PVR,-,yes,32
-304,HSPRG0,hypv,hypv,64
-305,HSPRG1,hypv,hypv,64
-306,HDSISR,hypv,hypv,32
-307,HDAR,hypv,hypv,64
-308,SPURR,hypv,yes,64
-309,PURR,hypv,yes,64
-310,HDEC,hypv,hypv,64
-313,HRMOR,hypv,hypv,64
-314,HSRR0,hypv,hypv,64
-315,HSRR1,hypv,hypv,64
-318,LPCR,hypv,hypv,64
-319,LPIDR,hypv,hypv,32
-336,HMER,hypv,hypv,64
-337,HMEER,hypv,hypv,64
-338,PCR,hypv,hypv,64
-339,HEIR,hypv,hypv,32
-349,AMOR,hypv,hypv,64
-446,TIR,-,yes,64
-464,PTCR,hypv,hypv,64
-704,SVSTATE,no,no,32
-720,PRTBL,yes,yes,64
-721,SVSRR0,yes,yes,32
-768,SIER,-,no,64
-769,MMCR2,no,no,64
-770,MMCRA,no,no,64
-771,PMC1,no,no,32
-772,PMC2,no,no,32
-773,PMC3,no,no,32
-774,PMC4,no,no,32
-775,PMC5,no,no,32
-776,PMC6,no,no,32
-779,MMCR0,no,no,64
-780,SIAR,-,no,64
-781,SDAR,-,no,64
-782,MMCR1,-,no,64
-784,SIER_priv,yes,yes,64
-785,MMCR2_priv,yes,yes,64
-786,MMCRA_priv,yes,yes,64
-787,PMC1_priv,yes,yes,32
-788,PMC2_priv,yes,yes,32
-789,PMC3_priv,yes,yes,32
-790,PMC4_priv,yes,yes,32
-791,PMC5_priv,yes,yes,32
-792,PMC6_priv,yes,yes,32
-795,MMCR0_priv,yes,yes,64
-796,SIAR_priv,yes,yes,64
-797,SDAR_priv,yes,yes,64
-798,MMCR1_priv,yes,yes,64
-800,BESCRS,no,no,64
-801,BESCRSU,no,no,32
-802,BESCRR,no,no,64
-803,BESCRRU,no,no,32
-804,EBBHR,no,no,64
-805,EBBRR,no,no,64
-806,BESCR,no,no,64
-808,reserved808,no,no,0
-809,reserved809,no,no,0
-810,reserved810,no,no,0
-811,reserved811,no,no,0
-815,TAR,no,no,64
-816,ASDR,hypv,hypv,64
-823,PSSCR,yes,yes,64
-848,IC,hypv,yes,64
-849,VTB,hypv,yes,64
-855,PSSCR_hypv,hypv,hypv,64
-896,PPR,no,no,64
-898,PPR32,no,no,32
-1023,PIR,-,yes,32
projects / libreriscv.git / commitdiff