+2018-06-14 Alan Modra <amodra@gmail.com>
+
+ * elf-bfd.h (struct elf_link_hash_table): Add "dynamic_relocs".
+ * elflink.c (_bfd_elf_init_2_index_sections): Comment fix.
+ (_bfd_elf_add_dynamic_entry): Set "dynamic_relocs".
+ (_bfd_elf_link_renumber_dynsyms): Exclude all section symbols when
+ "dynamic_relocs" is not set.
+ * elfxx-mips.c (count_section_dynsyms): Likewise.
+
2018-06-14 Alan Modra <amodra@gmail.com>
PR 23282
when linking against or generating a shared object. */
bfd_boolean dynamic_sections_created;
+ /* Whether dynamic relocations are present. */
+ bfd_boolean dynamic_relocs;
+
/* True if this target has relocatable executables, so needs dynamic
section symbols. */
bfd_boolean is_relocatable_executable;
for (p = output_bfd->sections; p ; p = p->next)
if ((p->flags & SEC_EXCLUDE) == 0
&& (p->flags & SEC_ALLOC) != 0
+ && elf_hash_table (info)->dynamic_relocs
&& !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p))
{
++dynsymcount;
if (! is_elf_hash_table (hash_table))
return FALSE;
+ if (tag == DT_RELA || tag == DT_REL)
+ hash_table->dynamic_relocs = TRUE;
+
bed = get_elf_backend_data (hash_table->dynobj);
s = bfd_get_linker_section (hash_table->dynobj, ".dynamic");
BFD_ASSERT (s != NULL);
asection *s;
/* Data first, since setting text_index_section changes
- _bfd_elf_link_omit_section_dynsym. */
+ _bfd_elf_omit_section_dynsym_default. */
for (s = output_bfd->sections; s != NULL; s = s->next)
if (((s->flags & (SEC_EXCLUDE | SEC_ALLOC | SEC_READONLY)) == SEC_ALLOC)
&& !_bfd_elf_omit_section_dynsym_default (output_bfd, info, s))
for (p = output_bfd->sections; p ; p = p->next)
if ((p->flags & SEC_EXCLUDE) == 0
&& (p->flags & SEC_ALLOC) != 0
+ && elf_hash_table (info)->dynamic_relocs
&& !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p))
++count;
}
+2018-06-14 Alan Modra <amodra@gmail.com>
+
+ * testsuite/ld-elf/readelf.exp: Delete DUMP and selection of
+ variant ver_def.vd.
+ * testsuite/ld-elf/ver_def-tic6x.vd: Delete.
+ * testsuite/ld-elf/shared.exp: Run most pr23161 and pr23162 tests for
+ linux, nacl and gnu targets.
+ * testsuite/ld-mips-elf/mips-elf.exp: Set base_syms to 1.
+ * testsuite/ld-elf/pr23161a.rd: Don't check reloc type. Allow any
+ order of __bss_start, _edata and _end.
+ * testsuite/ld-elf/pr23161b.rd: Don't check plt and dyn relocs.
+ Allow and order of __bss_start, _edata and _end.
+ * testsuite/ld-elf/pr23162.rd: Fail if __bss_start, _edata or _end
+ relocs are present rather than testing for no relocations.
+ * testsuite/ld-aarch64/gc-plt-relocs.d,
+ * testsuite/ld-aarch64/ifunc-1-local.d,
+ * testsuite/ld-aarch64/ifunc-1.d,
+ * testsuite/ld-aarch64/ifunc-2-local.d,
+ * testsuite/ld-aarch64/ifunc-2.d,
+ * testsuite/ld-aarch64/ifunc-21.d,
+ * testsuite/ld-aarch64/ifunc-3a.d,
+ * testsuite/ld-arm/farcall-mixed-lib-v4t.d,
+ * testsuite/ld-arm/farcall-mixed-lib.d,
+ * testsuite/ld-arm/gc-hidden-1.d,
+ * testsuite/ld-arm/tls-gdesc-got.d,
+ * testsuite/ld-arm/tls-lib-loc.d,
+ * testsuite/ld-arm/tls-longplt-lib.d,
+ * testsuite/ld-arm/tls-thumb1.d,
+ * testsuite/ld-cris/libdso-10.d,
+ * testsuite/ld-cris/libdso-11.d,
+ * testsuite/ld-cris/libdso-13b.d,
+ * testsuite/ld-cris/libdso-14.d,
+ * testsuite/ld-cris/libdso-15.d,
+ * testsuite/ld-cris/pic-gc-72.d,
+ * testsuite/ld-cris/pic-gc-73.d,
+ * testsuite/ld-cris/tls-gc-71.d,
+ * testsuite/ld-mips-elf/mips16-pic-4a.nd,
+ * testsuite/ld-mips-elf/pic-and-nonpic-3a.dd,
+ * testsuite/ld-mips-elf/pie-n32.d,
+ * testsuite/ld-mips-elf/pie-n64.d,
+ * testsuite/ld-mips-elf/pie-o32.d: Update for removed dynamic
+ section symbols.
+
2018-06-12 Hans-Peter Nilsson <hp@axis.com>
* testsuite/ld-cris/libdso-1.d: Correct recent address pattern update.
.*: file format elf64-(little|big)aarch64
DYNAMIC SYMBOL TABLE:
-0+8000 l d \.text 0+ \.text
0+8000 g DF \.text 0+4 _start
0+0000 D \*UND\* 0+ foo
0+8008 g DF \.text 0+ bar
#target: aarch64*-*-*
#...
-[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x1a0|0x1f0)@plt>
+0+(110|180) <__GI_foo>:
+#...
+[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x110|0x180)@plt>
#pass
#target: aarch64*-*-*
#...
-[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x1c0|0x208)@plt>
+0+(130|1a0) <foo>:
+#...
+[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(130|1a0)@plt>
#pass
#target: aarch64*-*-*
#...
-[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x1a0|0x1f0)@plt>
+0+(110|180) <__GI_foo>:
+#...
+[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(110|180)@plt>
[ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+x0, 0 <.*>
-[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #(0x190|0x1e0)
+[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #0x(100|170)
#pass
#target: aarch64*-*-*
#...
-[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x1c0|0x108)@plt>
+0+(130|1a0) <foo>:
+#...
+[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(130|1a0)@plt>
[ \t0-9a-f]+:[ \t0-9a-f]+adrp[ \t]+x0, 0 <.*>
-[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #(0x1b0|0x1f8)
+[ \t0-9a-f]+:[ \t0-9a-f]+add[ \t]+x0, x0, #0x(120|190)
#pass
[0-9a-f]+ .*
Contents of section .got.plt:
[0-9a-f]+ 0+ 0+ 0+ 0+ .*
- (102b8|10308) 0+ 0+ [0-9a-f]+ [0-9a-f]+ .*
+ 10298 0+ 0+ [0-9a-f]+ [0-9a-f]+ .*
Disassembly of section .text:
.* <bar>:
.*: 90000080 adrp x0, 10000 <.*>
- .*: .* ldr x0, \[x0, #(704|784)\]
+ .*: .* ldr x0, \[x0, #672\]
.*: d65f03c0 ret
#pass
#target: aarch64*-*-*
#...
-[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+(0x1e0|0x230)@plt>
+0+(150|1d0) <__GI_foo>:
+#...
+[ \t0-9a-f]+:[ \t0-9a-f]+bl[ \t0-9a-f]+<\*ABS\*\+0x(150|1d0)@plt>
#pass
.*: 4770 bx lr
#...
-.* <__app_func(_weak)?_from_thumb>:
+.* <__app_func_weak_from_thumb>:
.*: 4778 bx pc
.*: 46c0 nop ; \(mov r8, r8\)
- .*: e59fc000 ldr ip, \[pc\] ; 200038c <__app_func(_weak)?_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
- .*: fdffff(2|1)8 .word 0xfdffff(2|1)8
+ .*: fdffff34 .word 0xfdffff34
-.* <__app_func(_weak)?_from_thumb>:
+.* <__app_func_from_thumb>:
.*: 4778 bx pc
.*: 46c0 nop ; \(mov r8, r8\)
- .*: e59fc000 ldr ip, \[pc\] ; 200039c <__app_func(_weak)?_from_thumb\+0xc>
+ .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc>
.*: e08cf00f add pc, ip, pc
- .*: fdffff(0|1)8 .word 0xfdffff(0|1)8
+ .*: fdffff14 .word 0xfdffff14
.* <lib_func3>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; 20003ac <lib_func3\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func3\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: ffffffc5 .word 0xffffffc5
.* <lib_func2>:
- .*: e59fc004 ldr ip, \[pc, #4\] ; 20003bc <lib_func2\+0xc>
+ .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: feffff55 .word 0xfeffff55
.*: 4770 bx lr
#...
-.* <__app_func(_weak)?_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; 2000378 <__app_func(_weak)?_from_thumb\+0x8>
+.* <__app_func_weak_from_thumb>:
+ .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
- .*: fdffff(34|28) .word 0xfdffff(34|28)
+ .*: fdffff40 .word 0xfdffff40
-.* <__app_func(_weak)?_from_thumb>:
- .*: e59fc000 ldr ip, \[pc\] ; 2000384 <__app_func(_weak)?_from_thumb\+0x8>
+.* <__app_func_from_thumb>:
+ .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0x8>
.*: e08ff00c add pc, pc, ip
- .*: fdffff(1c|28) .word 0xfdffff(1c|28)
+ .*: fdffff28 .word 0xfdffff28
...
.*: file format elf32-.*
DYNAMIC SYMBOL TABLE:
-0+[0-9a-f]+ l d .text 0+ .text
0+ g DO \*ABS\* 0+ NS NS
Disassembly of section .text:
.*/tls-lib2-got.so: file format elf32-.*arm.*
architecture: arm.*, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
-start address 0x000082.0
+start address 0x0+8(1e8|220)
Disassembly of section .got:
-000103.0 <.*>:
- 103.0: 000102.8 .*
+0+10(2e8|320) <.*>:
+ 10(2e8|320): 00010(260|298) .*
...
- 103.c: 00000008 .*
- 103.c: R_ARM_TLS_DESC \*ABS\*
- 103.0: 00000000 .*
- 103.4: 0000000c .*
- 103.4: R_ARM_TLS_DESC \*ABS\*
- 103.8: 00000000 .*
- 103.c: 80000004 .*
- 103.c: R_ARM_TLS_DESC glob1
- 103.0: 00000000 .*
- 103.4: 80000006 .*
- 103.4: R_ARM_TLS_DESC ext2
- 103.8: 00000000 .*
- 103.c: 80000007 .*
- 103.c: R_ARM_TLS_DESC ext1
- 103.0: 00000000 .*
- 103.4: 80000009 .*
- 103.4: R_ARM_TLS_DESC glob2
+ 10(2f4|32c): 00000008 .*
+ 10(2f4|32c): R_ARM_TLS_DESC \*ABS\*
+ 10(2f8|330): 00000000 .*
+ 10(2fc|334): 0000000c .*
+ 10(2fc|334): R_ARM_TLS_DESC \*ABS\*
+ 10(300|338): 00000000 .*
+ 10(304|33c): 80000002 .*
+ 10(304|33c): R_ARM_TLS_DESC glob1
+ 10(308|340): 00000000 .*
+ 10(30c|344): 80000004 .*
+ 10(30c|344): R_ARM_TLS_DESC ext2
+ 10(310|348): 00000000 .*
+ 10(314|34c): 80000005 .*
+ 10(314|34c): R_ARM_TLS_DESC ext1
+ 10(318|350): 00000000 .*
+ 10(31c|354): 80000007 .*
+ 10(31c|354): R_ARM_TLS_DESC glob2
...
[0-9a-f]+ <.plt>:
[0-9a-f]+: e52de004 push {lr} ; .*
- [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; 8150 .*
+ [0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; 8128 .*
[0-9a-f]+: e08fe00e add lr, pc, lr
[0-9a-f]+: e5bef008 ldr pc, \[lr, #8\]!
- 8150: 000080cc .word 0x000080cc
- 8154: e08e0000 add r0, lr, r0
+ 8128: 000080cc .word 0x000080cc
+ 812c: e08e0000 add r0, lr, r0
[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
[0-9a-f]+: e12fff11 bx r1
[0-9a-f]+: e52d2004 push {r2} ; .*
- 8164: e59f200c ldr r2, \[pc, #12\] ; 8178 .*
- [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; 817c .*
+ 813c: e59f200c ldr r2, \[pc, #12\] ; 8150 .*
+ [0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; 8154 .*
[0-9a-f]+: e79f2002 ldr r2, \[pc, r2\]
[0-9a-f]+: e081100f add r1, r1, pc
[0-9a-f]+: e12fff12 bx r2
- 8178: 000080bc .word 0x000080bc
- 817c: 000080a4 .word 0x000080a4
+ 8150: 000080bc .word 0x000080bc
+ 8154: 000080a4 .word 0x000080a4
Disassembly of section .text:
[0-9a-f]+ <foo>:
- [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; 818c .*
- [0-9a-f]+: fafffff2 blx 8154 <.*>
+ [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; 8164 .*
+ [0-9a-f]+: fafffff2 blx 812c <.*>
[0-9a-f]+: e1a00000 nop ; .*
- 818c: 000080a0 .word 0x000080a0
+ 8164: 000080a0 .word 0x000080a0
Disassembly of section .plt:
-00008198 <.plt>:
- 8198: e52de004 push {lr} ; .*
- 819c: e59fe004 ldr lr, \[pc, #4\] ; .*
- 81a0: e08fe00e add lr, pc, lr
- 81a4: e5bef008 ldr pc, \[lr, #8\]!
- 81a8: 000080e0 .word 0x000080e0
- 81ac: e08e0000 add r0, lr, r0
- 81b0: e5901004 ldr r1, \[r0, #4\]
- 81b4: e12fff11 bx r1
- 81b8: e52d2004 push {r2} ; .*
- 81bc: e59f200c ldr r2, \[pc, #12\] ; .*
- 81c0: e59f100c ldr r1, \[pc, #12\] ; .*
- 81c4: e79f2002 ldr r2, \[pc, r2\]
- 81c8: e081100f add r1, r1, pc
- 81cc: e12fff12 bx r2
- 81d0: 000080d8 .word 0x000080d8
- 81d4: 000080b8 .word 0x000080b8
+00008170 <.plt>:
+.*: e52de004 push {lr} ; .*
+.*: e59fe004 ldr lr, \[pc, #4\] ; .*
+.*: e08fe00e add lr, pc, lr
+.*: e5bef008 ldr pc, \[lr, #8\]!
+.*: 000080e0 .word 0x000080e0
+.*: e08e0000 add r0, lr, r0
+.*: e5901004 ldr r1, \[r0, #4\]
+.*: e12fff11 bx r1
+.*: e52d2004 push {r2} ; .*
+.*: e59f200c ldr r2, \[pc, #12\] ; .*
+.*: e59f100c ldr r1, \[pc, #12\] ; .*
+.*: e79f2002 ldr r2, \[pc, r2\]
+.*: e081100f add r1, r1, pc
+.*: e12fff12 bx r2
+.*: 000080d8 .word 0x000080d8
+.*: 000080b8 .word 0x000080b8
Disassembly of section .text:
-000081d8 <text>:
- 81d8: e59f0004 ldr r0, \[pc, #4\] ; .*
- 81dc: fafffff2 blx 81ac .*
- 81e0: e1a00000 nop ; .*
- 81e4: 000080b4 .word 0x000080b4
- 81e8: 4801 ldr r0, \[pc, #4\] ; .*
- 81ea: f7ff efe0 blx 81ac <.*>
- 81ee: bf00 nop
- 81f0: 000080a5 .word 0x000080a5
+000081b0 <text>:
+.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: fafffff2 blx .* <\.plt\+0x14>
+.*: e1a00000 nop ; .*
+.*: 000080b4 .word 0x000080b4
+.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: f7ff efe0 blx .* <\.plt\+0x14>
+.*: bf00 nop
+.*: 000080a5 .word 0x000080a5
Disassembly of section .foo:
04001000 <foo>:
- 4001000: e59f0004 ldr r0, \[pc, #4\] ; .*
- 4001004: fa000009 blx 4001030 .*
- 4001008: e1a00000 nop ; .*
- 400100c: fc00f28c .word 0xfc00f28c
- 4001010: e59f0004 ldr r0, \[pc, #4\] ; .*
- 4001014: fa000005 blx 4001030 .*
- 4001018: e1a00000 nop ; .*
- 400101c: fc00f284 .word 0xfc00f284
- 4001020: 4801 ldr r0, \[pc, #4\] ; .*
- 4001022: f000 e806 blx 4001030 .*
- 4001026: bf00 nop
- 4001028: fc00f26d .word 0xfc00f26d
- 400102c: 00000000 .word 0x00000000
+.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: fa000009 blx 4001030 .*
+.*: e1a00000 nop ; .*
+.*: fc00f264 .word 0xfc00f264
+.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: fa000005 blx 4001030 .*
+.*: e1a00000 nop ; .*
+.*: fc00f25c .word 0xfc00f25c
+.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: f000 e806 blx 4001030 .*
+.*: bf00 nop
+.*: fc00f245 .word 0xfc00f245
+.*: 00000000 .word 0x00000000
04001030 <__unnamed_veneer>:
- 4001030: e59f1000 ldr r1, \[pc\] ; .*
- 4001034: e08ff001 add pc, pc, r1
- 4001038: fc007170 .word 0xfc007170
- 400103c: 00000000 .word 0x00000000
+.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e08ff001 add pc, pc, r1
+.*: fc007148 .word 0xfc007148
+.*: 00000000 .word 0x00000000
Disassembly of section .plt:
-00008164 <.plt>:
- 8164: e52de004 push {lr} ; .*
- 8168: e59fe004 ldr lr, \[pc, #4\] ; .*
- 816c: e08fe00e add lr, pc, lr
- 8170: e5bef008 ldr pc, \[lr, #8\]!
- 8174: 000080f0 .word 0x000080f0
- 8178: e08e0000 add r0, lr, r0
- 817c: e5901004 ldr r1, \[r0, #4\]
- 8180: e12fff11 bx r1
- 8184: e52d2004 push {r2} ; .*
- 8188: e59f200c ldr r2, \[pc, #12\] ; .*
- 818c: e59f100c ldr r1, \[pc, #12\] ; .*
- 8190: e79f2002 ldr r2, \[pc, r2\]
- 8194: e081100f add r1, r1, pc
- 8198: e12fff12 bx r2
- 819c: 000080e8 .word 0x000080e8
- 81a0: 000080c8 .word 0x000080c8
+0000813c <.plt>:
+.*: e52de004 push {lr} ; .*
+.*: e59fe004 ldr lr, \[pc, #4\] ; .*
+.*: e08fe00e add lr, pc, lr
+.*: e5bef008 ldr pc, \[lr, #8\]!
+.*: 000080f0 .word 0x000080f0
+.*: e08e0000 add r0, lr, r0
+.*: e5901004 ldr r1, \[r0, #4\]
+.*: e12fff11 bx r1
+.*: e52d2004 push {r2} ; .*
+.*: e59f200c ldr r2, \[pc, #12\] ; .*
+.*: e59f100c ldr r1, \[pc, #12\] ; .*
+.*: e79f2002 ldr r2, \[pc, r2\]
+.*: e081100f add r1, r1, pc
+.*: e12fff12 bx r2
+.*: 000080e8 .word 0x000080e8
+.*: 000080c8 .word 0x000080c8
Disassembly of section .text:
-000081a8 <text>:
- 81a8: e59f0004 ldr r0, \[pc, #4\] ; .*
- 81ac: ebfffff1 bl 8178 .*
- 81b0: e1a00000 nop ; .*
- 81b4: 000080c0 .word 0x000080c0
- 81b8: 4801 ldr r0, \[pc, #4\] ; .*
- 81ba: f000 f805 bl 81c8 .*
- 81be: 46c0 nop ; .*
- 81c0: 000080b1 .word 0x000080b1
- 81c4: 00000000 .word 0x00000000
+00008180 <text>:
+.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: ebfffff1 bl .* <\.plt\+0x14>
+.*: e1a00000 nop ; .*
+.*: 000080c0 .word 0x000080c0
+.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: f000 f805 bl .* <__unnamed_veneer>
+.*: 46c0 nop ; .*
+.*: 000080b1 .word 0x000080b1
+.*: 00000000 .word 0x00000000
-000081c8 <__unnamed_veneer>:
- 81c8: 4778 bx pc
- 81ca: 46c0 nop ; .*
- 81cc: e59f1000 ldr r1, \[pc\] ; .*
- 81d0: e081f00f add pc, r1, pc
- 81d4: ffffffa0 .word 0xffffffa0
+000081a0 <__unnamed_veneer>:
+.*: 4778 bx pc
+.*: 46c0 nop ; .*
+.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e081f00f add pc, r1, pc
+.*: ffffffa0 .word 0xffffffa0
Disassembly of section .foo:
04001000 <foo>:
- 4001000: e59f0004 ldr r0, \[pc, #4\] ; .*
- 4001004: eb000009 bl 4001030 .*
- 4001008: e1a00000 nop ; .*
- 400100c: fc00f268 .word 0xfc00f268
- 4001010: e59f0004 ldr r0, \[pc, #4\] ; .*
- 4001014: eb000005 bl 4001030 .*
- 4001018: e1a00000 nop ; .*
- 400101c: fc00f260 .word 0xfc00f260
- 4001020: 4801 ldr r0, \[pc, #4\] ; .*
- 4001022: f000 f80b bl 400103c .*
- 4001026: 46c0 nop ; .*
- 4001028: fc00f249 .word 0xfc00f249
- 400102c: 00000000 .word 0x00000000
+.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: eb000009 bl 4001030 .*
+.*: e1a00000 nop ; .*
+.*: fc00f240 .word 0xfc00f240
+.*: e59f0004 ldr r0, \[pc, #4\] ; .*
+.*: eb000005 bl 4001030 .*
+.*: e1a00000 nop ; .*
+.*: fc00f238 .word 0xfc00f238
+.*: 4801 ldr r0, \[pc, #4\] ; .*
+.*: f000 f80b bl 400103c .*
+.*: 46c0 nop ; .*
+.*: fc00f221 .word 0xfc00f221
+.*: 00000000 .word 0x00000000
04001030 <__unnamed_veneer>:
- 4001030: e59f1000 ldr r1, \[pc\] ; .*
- 4001034: e08ff001 add pc, pc, r1
- 4001038: fc00713c .word 0xfc00713c
+.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e08ff001 add pc, pc, r1
+.*: fc007114 .word 0xfc007114
0400103c <__unnamed_veneer>:
- 400103c: 4778 bx pc
- 400103e: 46c0 nop ; .*
- 4001040: e59f1000 ldr r1, \[pc\] ; .*
- 4001044: e081f00f add pc, r1, pc
- 4001048: fc00712c .word 0xfc00712c
- 400104c: 00000000 .word 0x00000000
+.*: 4778 bx pc
+.*: 46c0 nop ; .*
+.*: e59f1000 ldr r1, \[pc\] ; .*
+.*: e081f00f add pc, r1, pc
+.*: fc007104 .word 0xfc007104
+.*: 00000000 .word 0x00000000
Program Header:
LOAD off 0x0+ vaddr 0x0+ paddr 0x0+ align 2\*\*13
- filesz 0x0+e8 memsz 0x0+e8 flags r-x
- LOAD off 0x0+e8 vaddr 0x0+20e8 paddr 0x0+20e8 align 2\*\*13
+ filesz 0x0+d4 memsz 0x0+d4 flags r-x
+ LOAD off 0x0+d4 vaddr 0x0+20d4 paddr 0x0+20d4 align 2\*\*13
filesz 0x0+64 memsz 0x0+64 flags rw-
- DYNAMIC off 0x0+e8 vaddr 0x0+20e8 paddr 0x0+20e8 align 2\*\*2
+ DYNAMIC off 0x0+d4 vaddr 0x0+20d4 paddr 0x0+20d4 align 2\*\*2
filesz 0x0+58 memsz 0x0+58 flags rw-
Dynamic Section:
HASH.*0x0*94
- STRTAB.*0x0*dc
- SYMTAB.*0x0*ac
+ STRTAB.*0x0*c8
+ SYMTAB.*0x0*a8
STRSZ.*0x0*7
SYMENT.*0x0*10
private flags = 2: \[v32\]
Sections:
Idx Name Size VMA LMA File off Algn
- 0 \.hash 0+18 0+94 0+94 0+94 2\*\*2
+ 0 \.hash 0+14 0+94 0+94 0+94 2\*\*2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 \.dynsym 0+30 0+ac 0+ac 0+ac 2\*\*2
+ 1 \.dynsym 0+20 0+a8 0+a8 0+a8 2\*\*2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 2 \.dynstr 0+7 0+dc 0+dc 0+dc 2\*\*0
+ 2 \.dynstr 0+7 0+c8 0+c8 0+c8 2\*\*0
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 \.text 0+4 0+e4 0+e4 0+e4 2\*\*1
+ 3 \.text 0+4 0+d0 0+d0 0+d0 2\*\*1
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 4 \.dynamic 0+58 0+20e8 0+20e8 0+e8 2\*\*2
+ 4 \.dynamic 0+58 0+20d4 0+20d4 0+d4 2\*\*2
CONTENTS, ALLOC, LOAD, DATA
- 5 \.got 0+c 0+2140 0+2140 0+140 2\*\*2
+ 5 \.got 0+c 0+212c 0+212c 0+12c 2\*\*2
CONTENTS, ALLOC, LOAD, DATA
DYNAMIC SYMBOL TABLE:
#...
-0+144 g DF \.text 0+8 dsofn3
+0+130 g DF \.text 0+8 dsofn3
#...
-0+140 g DF \.text 0+2 dsofn
+0+12c g DF \.text 0+2 dsofn
#...
Contents of section \.rela\.plt:
- 0100 d0210000 0b030000 00000000 .*
+.* bc210000 0b020000 00000000 .*
Contents of section \.plt:
- 010c 84e20401 7e7a3f7a 04f26ffa bf09b005 .*
- 011c 00000000 00000000 00006f0d 0c000000 .*
- 012c 6ffabf09 b0053f7e 00000000 bf0ed4ff .*
- 013c ffffb005 .*
+.* 84e20401 7e7a3f7a 04f26ffa bf09b005 .*
+.* 00000000 00000000 00006f0d 0c000000 .*
+.* 6ffabf09 b0053f7e 00000000 bf0ed4ff .*
+.* ffffb005 .*
Contents of section \.text:
- 0140 b0050000 bfbee2ff ffffb005 .*
+.* b0050000 bfbee2ff ffffb005 .*
Contents of section \.dynamic:
#...
Contents of section \.got:
- 21c4 4c210000 00000000 00000000 32010000 .*
+.* 38210000 00000000 00000000 1e010000 .*
# script hiding the function called pcrel-without-plt. There should
# be no warning, no relocations in the output and no TEXTREL marking.
-Dynamic section at offset 0x150 contains 9 entries:
+Dynamic section at offset .* contains 9 entries:
Tag Type Name/Value
0x00000004 \(HASH\) .*
0x00000005 \(STRTAB\) .*
# Checking that a bsr to a non-PLT-decorated nonvisible function
# doesn't make the DSO textrel.
-Dynamic section at offset 0x110 contains 6 entries:
+Dynamic section at offset .* contains 6 entries:
Tag[ ]+Type[ ]+Name/Value
0x0+4 \(HASH\)[ ]+0x94
- 0x0+5 \(STRTAB\)[ ]+0xf0
- 0x0+6 \(SYMTAB\)[ ]+0xb0
+ 0x0+5 \(STRTAB\)[ ]+0xdc
+ 0x0+6 \(SYMTAB\)[ ]+0xac
0x0+a \(STRSZ\)[ ]+14 \(bytes\)
0x0+b \(SYMENT\)[ ]+16 \(bytes\)
0x0+ \(NULL\)[ ]+0x0
DYNAMIC SYMBOL TABLE:
#...
-0+2238 g[ ]+DO .data[ ]+0+4 TST3[ ]+__expobj2
-0+1ba g[ ]+DF .text[ ]+0+2 TST3[ ]+__expfn2
-0+1ba w[ ]+DF .text[ ]+0+2 TST3[ ]+expfn2
-0+2238 w[ ]+DO .data[ ]+0+4 TST3[ ]+expobj2
+0+2220 g[ ]+DO .data[ ]+0+4 TST3[ ]+__expobj2
+0+1a2 g[ ]+DF .text[ ]+0+2 TST3[ ]+__expfn2
+0+1a2 w[ ]+DF .text[ ]+0+2 TST3[ ]+expfn2
+0+2220 w[ ]+DO .data[ ]+0+4 TST3[ ]+expobj2
#...
Contents of section .text:
- 01b8 0f050f05 .*
+.* 0f050f05 .*
#...
Contents of section .got:
- 222c bc210000 00000000 00000000 .*
+.* a4210000 00000000 00000000 .*
Contents of section .data:
- 2238 00000000 .*
+.* 00000000 .*
Contents of section .dynstr:
#...
Contents of section .text:
- 0121 0f050f05 .*
+.* 0f050f05 .*
Contents of section .dynamic:
- 2128 .*
+ 2114 .*
#...
Contents of section .got:
- 2180 28210000 00000000 00000000 .*
+.* 14210000 00000000 00000000 .*
Contents of section .data:
- 218c 00000000 .*
+.* 00000000 .*
Contents of section .dynstr:
#...
Contents of section .text:
- 0121 0f050f05 .*
+.* 0f050f05 .*
Contents of section .dynamic:
+ 2114 .*
#...
Contents of section .got:
- 2180 28210000 00000000 00000000 .*
+.* 14210000 00000000 00000000 .*
Contents of section .data:
- 218c 00000000 .*
+.* 00000000 .*
filesz 0x0+80 memsz 0x0+80 flags r--
#...
DYNAMIC SYMBOL TABLE:
-0+132 l d \.text 0+ \.text
-0+2138 l d \.tdata 0+ \.tdata
-0+132 g DF \.text 0+2 _init
+0+10a g DF \.text 0+2 _init
0+ g D .tdata 0+80 tls128
DYNAMIC RELOCATION RECORDS \(none\)
#...
Contents of section \.text:
- 0132 0f050000 .*
+ 010a 0f050000 .*
#...
Contents of section \.got:
- 2218 b8210000 00000000 00000000 .*
+.* 90210000 00000000 00000000 .*
Relocation section '\.rel(a|)\.dyn' at offset 0x[0-9a-f]+ contains [0-9]+ entries:
- +Offset +Info +Type +Sym.* Value +Sym.* Name( \+ Addend|)
#...
-[a-f0-9]+ +[0-9a-f]+ +R_.*_GLOB_DAT +[a-f0-9]+ +__bss_start(@@FOO|)( \+ 0|)
+.* _?_(_bss_start|edata|end)(@@FOO|)( \+ 0|)
#...
-[a-f0-9]+ +[0-9a-f]+ +R_.*_GLOB_DAT +[a-f0-9]+ +_edata(@@FOO|)( \+ 0|)
+.* _?_(_bss_start|edata|end)(@@FOO|)( \+ 0|)
#...
-[a-f0-9]+ +[0-9a-f]+ +R_.*_GLOB_DAT +[a-f0-9]+ +_end(@@FOO|)( \+ 0|)
+.* _?_(_bss_start|edata|end)(@@FOO|)( \+ 0|)
#...
Symbol table '\.dynsym' contains [0-9]+ entries:
- +Num: +Value +Size Type +Bind +Vis +Ndx Name
- +0: 0+ +0 +NOTYPE +LOCAL +DEFAULT +UND +
#...
- +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_edata(@@FOO|)
+ +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_?_(_bss_start|edata|end)(@@FOO|)
#...
- +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_end(@@FOO|)
+ +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_?_(_bss_start|edata|end)(@@FOO|)
#...
- +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +__bss_start(@@FOO|)
+ +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_?_(_bss_start|edata|end)(@@FOO|)
#...
-Relocation section '\.rel(a|)\.plt' at offset 0x[0-9a-f]+ contains 1 entry:
- +Offset +Info +Type +Sym.* Value +Sym.* Name( \+ Addend|)
-[a-f0-9]+ +[0-9a-f]+ +R_.*_JUMP_SLOT +[a-f0-9]+ +foo(@FOO|)( \+ 0|)
-
-Symbol table '\.dynsym' contains [0-9]+ entries:
- +Num: +Value +Size Type +Bind +Vis +Ndx Name
- +0: 0+ +0 +NOTYPE +LOCAL +DEFAULT +UND +
#...
- +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_edata
+ +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT.* [0-9]+ +_?_(_bss_start|edata|end)
#...
- +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +_end
-#...
- +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT +[0-9]+ +__bss_start
+ +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT.* [0-9]+ +_?_(_bss_start|edata|end)
#...
+ +[0-9]+: +[a-f0-9]+ +0 +NOTYPE +GLOBAL +DEFAULT.* [0-9]+ +_?_(_bss_start|edata|end)
+#pass
-There are no relocations in this file\.
-
-Symbol table '\.dynsym' contains 1 entry:
- +Num: +Value +Size Type +Bind +Vis +Ndx Name
- +0: 0+ +0 +NOTYPE +LOCAL +DEFAULT +UND +
+#failif
+#...
+[a-f0-9]+ +[0-9a-f]+ +R_[^ ]* +[a-f0-9]+ _?_(_bss_start|edata|end)(@@FOO|)( \+ 0|)
+#...
}
# This target requires a non-default emulation for successful shared
-# library/executable builds, and has dump variances.
+# library/executable builds.
set LFLAGS ""
-set DUMP ""
if [istarget "tic6x-*-*"] {
append LFLAGS " -melf32_tic6x_le"
- set DUMP "-tic6x"
}
if [check_shared_lib_support] {
--hash-style=sysv --version-script=ver_def.ver" \
"" "" \
{ver_def.s} \
- [list [list readelf --version-info ver_def$DUMP.vd]] \
+ [list [list readelf --version-info ver_def.vd]] \
"ver_def"]]
}
mix_pic_and_non_pic [list "arm*-*-*" "aarch64*-*-*"] "" "" "pr19719"
mix_pic_and_non_pic [] "-fPIE" "-pie" "pr19719pie"
-if { ([istarget "i?86-*-*"]
- || [istarget "x86_64-*-*"]) } {
+set AFLAGS_PIE ""
+if { [istarget "i?86-*-*"]
+ || [istarget "x86_64-*-*"] } {
+ set AFLAGS_PIE "-mrelax-relocations=yes"
+}
+
+if { ([istarget "*-*-linux*"]
+ || [istarget "*-*-nacl*"]
+ || [istarget "*-*-gnu*"])
+ && ![istarget "mips*-*-*"] } {
run_ld_link_tests [list \
[list \
"Build libpr23162a.so" \
"Build pr23162a" \
"-pie --no-as-needed tmpdir/libpr23162a.so" \
"" \
- "-mrelax-relocations=yes" \
+ $AFLAGS_PIE \
{ pr23162b.c } \
- {{readelf {--dyn-syms -rW} pr23162.rd}} \
+ {{readelf {-rW} pr23162.rd}} \
"pr23162a" \
"-fPIC -O0" \
] \
"Build pr23162b" \
"-pie --no-as-needed tmpdir/libpr23162b.so" \
"" \
- "-mrelax-relocations=yes" \
+ $AFLAGS_PIE \
{ pr23162b.c } \
- {{readelf {--dyn-syms -rW} pr23162.rd}} \
+ {{readelf {-rW} pr23162.rd}} \
"pr23162b" \
"-fPIC -O0" \
] \
"Build pr23161a" \
"-pie --no-as-needed tmpdir/libpr23161a.so" \
"" \
- "-mrelax-relocations=yes" \
+ $AFLAGS_PIE \
{ pr23161b.c } \
{{readelf {--dyn-syms -rW} pr23161b.rd}} \
"pr23161a" \
"Build pr23161b" \
"-pie --no-as-needed tmpdir/libpr23161b.so" \
"" \
- "-mrelax-relocations=yes" \
+ $AFLAGS_PIE \
{ pr23161b.c } \
{{readelf {--dyn-syms -rW} pr23161b.rd}} \
"pr23161b" \
"-fPIC -O0" \
] \
+ ]
+}
+
+if { [istarget "i?86-*-*"]
+ || [istarget "x86_64-*-*"] } {
+ run_ld_link_tests [list \
[list \
"Build libpr23161c.so" \
"-shared" \
"Build pr23161c" \
"-pie --no-as-needed tmpdir/libpr23161c.so" \
"" \
- "-mrelax-relocations=yes" \
+ $AFLAGS_PIE \
{ pr23161b.c } \
{{readelf {--dyn-syms -rW} pr23161d.rd}} \
"pr23161c" \
+++ /dev/null
-# Verify correct version information output from `readelf' and that there
-# is no:
-#
-# Version definition past end of section
-#
-# line at the end in particular (hence #pass must not be used here).
-
-# TI C6X special variant covering an extra `.got.plt' dynamic symbol
-# table entry and consequently its `.gnu.version' record made as a
-# result of unusual processing in `elf32_tic6x_link_omit_section_dynsym'.
-
-Version symbols section '\.gnu\.version' contains 5 entries:
- Addr: [0-9a-f]+ +Offset: 0x[0-9a-f]+ +Link: 2 \(\.dynsym\)
- +000: +0 \(\*local\*\) +0 \(\*local\*\) +2 \(ver_foo\) +1 \(\*global\*\) +
- +004: +2 \(ver_foo\) +
-
-Version definition section '\.gnu\.version_d' contains 2 entries:
- +Addr: 0x[0-9a-f]+ +Offset: 0x[0-9a-f]+ +Link: 3 \(\.dynstr\)
- +000000: Rev: 1 +Flags: BASE +Index: 1 +Cnt: 1 +Name: ver_def
- +0x001c: Rev: 1 +Flags: none +Index: 2 +Cnt: 1 +Name: ver_foo
if {[istarget mips*-*-linux*]} {
# The number of symbols that are always included in the symbol table
- # for these tests. The 2 are:
- #
+ # for these tests.
# the null symbol entry
- # the .MIPS.stubs section symbol
- set base_syms 2
+ set base_syms 1
foreach { isa aflag lflag suffix } \
{ MIPS -march=mips1 "" "" \
microMIPS -mmicromips "" -micromips \
-Symbol table '\.dynsym' contains 6 entries:
+Symbol table '\.dynsym' contains 5 entries:
+Num: +Value +Size +Type +Bind +Vis +Ndx +Name
+0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND
- +1: 00040400 +0 +SECTION +LOCAL +DEFAULT +.*
- +2: 00040420 +12 +FUNC +GLOBAL +DEFAULT +.* f1@@V1
- +3: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +ABS V1
- +4: 00040408 +8 +FUNC +GLOBAL +DEFAULT +.* f3@@V1
- +5: 00040400 +8 +FUNC +GLOBAL +DEFAULT +.* f2@@V1
+ +1: 00040420 +12 +FUNC +GLOBAL +DEFAULT +.* f1@@V1
+ +2: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +ABS V1
+ +3: 00040408 +8 +FUNC +GLOBAL +DEFAULT +.* f3@@V1
+ +4: 00040400 +8 +FUNC +GLOBAL +DEFAULT +.* f2@@V1
#pass
c00: 8f998010 lw t9,-32752\(gp\)
c04: 03e07825 move t7,ra
c08: 0320f809 jalr t9
- c0c: 24180004 li t8,4
+ c0c: 24180003 li t8,3
\.\.\.
Dynamic section at offset 0x180 contains 17 entries:
Tag * Type * Name/Value
0x00000004 \(HASH\) * 0x230
- 0x00000005 \(STRTAB\) * 0x28c
- 0x00000006 \(SYMTAB\) * 0x24c
+ 0x00000005 \(STRTAB\) * 0x278
+ 0x00000006 \(SYMTAB\) * 0x248
0x0000000a \(STRSZ\) * 28 \(bytes\)
0x0000000b \(SYMENT\) * 16 \(bytes\)
- 0x70000035 \(MIPS_RLD_MAP_REL\) * 0x10118
+ 0x70000035 \(MIPS_RLD_MAP_REL\) * 0x10108
0x00000015 \(DEBUG\) * 0x0
- 0x00000003 \(PLTGOT\) * 0x102d0
+ 0x00000003 \(PLTGOT\) * 0x102c0
0x70000001 \(MIPS_RLD_VERSION\) * 1
0x70000005 \(MIPS_FLAGS\) * NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) * 0x0
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x70000011 \(MIPS_SYMTABNO\) * 4
+ 0x70000011 \(MIPS_SYMTABNO\) * 3
0x70000012 \(MIPS_UNREFEXTNO\) * 13
- 0x70000013 \(MIPS_GOTSYM\) * 0x4
+ 0x70000013 \(MIPS_GOTSYM\) * 0x3
0x6ffffffb \(FLAGS_1\) * Flags: PIE
0x00000000 \(NULL\) * 0x0
Dynamic section at offset 0x208 contains 17 entries:
Tag * Type * Name/Value
0x0+00000004 \(HASH\) * 0x368
- 0x0+00000005 \(STRTAB\) * 0x3e8
- 0x0+00000006 \(SYMTAB\) * 0x388
+ 0x0+00000005 \(STRTAB\) * 0x3c8
+ 0x0+00000006 \(SYMTAB\) * 0x380
0x0+0000000a \(STRSZ\) * 28 \(bytes\)
0x0+0000000b \(SYMENT\) * 24 \(bytes\)
- 0x0+70000035 \(MIPS_RLD_MAP_REL\) * 0x101e8
+ 0x0+70000035 \(MIPS_RLD_MAP_REL\) * 0x101c8
0x0+00000015 \(DEBUG\) * 0x0
- 0x0+00000003 \(PLTGOT\) * 0x10450
+ 0x0+00000003 \(PLTGOT\) * 0x10430
0x0+70000001 \(MIPS_RLD_VERSION\) * 1
0x0+70000005 \(MIPS_FLAGS\) * NOTPOT
0x0+70000006 \(MIPS_BASE_ADDRESS\) * 0x0
0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x0+70000011 \(MIPS_SYMTABNO\) * 4
+ 0x0+70000011 \(MIPS_SYMTABNO\) * 3
0x0+70000012 \(MIPS_UNREFEXTNO\) * 13
- 0x0+70000013 \(MIPS_GOTSYM\) * 0x4
+ 0x0+70000013 \(MIPS_GOTSYM\) * 0x3
0x0+6ffffffb \(FLAGS_1\) * Flags: PIE
0x0+00000000 \(NULL\) * 0x0
Dynamic section at offset 0x178 contains 17 entries:
Tag * Type * Name/Value
0x00000004 \(HASH\) * 0x228
- 0x00000005 \(STRTAB\) * 0x284
- 0x00000006 \(SYMTAB\) * 0x244
+ 0x00000005 \(STRTAB\) * 0x270
+ 0x00000006 \(SYMTAB\) * 0x240
0x0000000a \(STRSZ\) * 28 \(bytes\)
0x0000000b \(SYMENT\) * 16 \(bytes\)
- 0x70000035 \(MIPS_RLD_MAP_REL\) * 0x10110
+ 0x70000035 \(MIPS_RLD_MAP_REL\) * 0x10100
0x00000015 \(DEBUG\) * 0x0
- 0x00000003 \(PLTGOT\) * 0x102c0
+ 0x00000003 \(PLTGOT\) * 0x102b0
0x70000001 \(MIPS_RLD_VERSION\) * 1
0x70000005 \(MIPS_FLAGS\) * NOTPOT
0x70000006 \(MIPS_BASE_ADDRESS\) * 0x0
0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
- 0x70000011 \(MIPS_SYMTABNO\) * 4
+ 0x70000011 \(MIPS_SYMTABNO\) * 3
0x70000012 \(MIPS_UNREFEXTNO\) * 13
- 0x70000013 \(MIPS_GOTSYM\) * 0x4
+ 0x70000013 \(MIPS_GOTSYM\) * 0x3
0x6ffffffb \(FLAGS_1\) * Flags: PIE
0x00000000 \(NULL\) * 0x0
projects / binutils-gdb.git / commitdiff