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Update CHANGELOG with "synth -abc9"
authorEddie Hung <eddie@fpgeh.com>
Thu, 13 Jun 2019 16:15:30 +0000 (09:15 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 13 Jun 2019 16:15:30 +0000 (09:15 -0700)
CHANGELOG patch | blob | history

diff --git a/CHANGELOG b/CHANGELOG
index 139f71672b74ef26b2a663169c4b14a99dca34aa..44e32c6a82bcb393bbc6b8aada33187059001ccf 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -20,6 +20,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
+    - Added "synth -abc9" (experimental)
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"