fhdl/verilog: fix dummy signal initial event

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index ee42066283f96f56ff15aec52a16e39e38f9cd54..bc050441443f3324159959a6077d8e35464ae561 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -184,7 +184,8 @@ def _printcomb(f, ns, display_run):
                syn_on = "// synthesis translate_on\n"
                dummy_s = Signal(name_override="dummy_s")
                r += syn_off
-               r += "reg " + _printsig(ns, dummy_s) + " = 1'd0;\n"
+               r += "reg " + _printsig(ns, dummy_s) + ";\n"
+               r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
                r += syn_on
 
                groups = group_by_targets(f.comb)