svp64_decode (char *str, struct svp64_ctx *svp64)
{
char *opc;
+ size_t opclen;
+ char *args;
+ size_t argslen;
char *iter;
const struct svp64_record *record;
+ char *base = str;
str += (sizeof ("sv.") - 1);
if (! ISALPHA (*str))
opc = str;
for (; ! ISSPACE (*str) && *str != SVP64_SEP && *str != '\0'; ++str)
;
+ opclen = (str - opc);
if (*str != '\0')
*str++ = '\0';
for (; (iter = svp64_decode_mode (str, svp64)) != NULL; str = iter)
;
+
+ args = str;
+ argslen = strlen (args);
+
+ memmove (base, opc, opclen);
+ base[opclen] = ' ';
+ memmove ((base + opclen + 1), args, argslen);
+ base[opclen + 1 + argslen] = '\0';
}
static void
svp64_decode (str, &svp64);
svp64_validate_and_fix (&svp64);
- as_warn (_("opcode ignored (desc=%p)"), svp64.desc);
- memcpy (str, "nop", sizeof ("nop"));
- md_assemble (str);
+ ppc_assemble (str, &svp64);
}
#include "libxcoff.h"
#endif
+struct svp64_ctx;
+
+static void
+ppc_assemble (char *str, struct svp64_ctx *svp64 ATTRIBUTE_UNUSED);
+
#include "tc-ppc-svp64.c"
/* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
/* This routine is called for each instruction to be assembled. */
-void
-md_assemble (char *str)
+static void
+ppc_assemble (char *str, struct svp64_ctx *svp64 ATTRIBUTE_UNUSED)
{
char *s;
const struct powerpc_opcode *opcode;
{
if (is_svp64_insn (str))
{
+ *(s - 1) = ' '; /* restore the original string */
svp64_assemble (str);
return;
}
}
}
+void
+md_assemble (char *str)
+{
+ ppc_assemble (str, NULL);
+}
\f
#ifdef OBJ_ELF
/* For ELF, add support for SHT_ORDERED. */