aarch64: Add few missing system registers

This patch adds few missing system registers to GAS: LORC_EL1,
LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2.

gas/ChangeLog:

2021-03-02  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
	* testsuite/gas/aarch64/illegal-sysreg-7.l: New test.
	* testsuite/gas/aarch64/illegal-sysreg-7.s: New test.
	* testsuite/gas/aarch64/sysreg-7.d: New test.
	* testsuite/gas/aarch64/sysreg-7.s: New test.

opcodes/ChangeLog:

2021-03-02  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
	icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 01161d5000ca23cde4085567712dfc90051b660b..79332f0f5dc1de3bbc45af3c0fca5fe94c74524d 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
+       * testsuite/gas/aarch64/illegal-sysreg-7.l: New test.
+       * testsuite/gas/aarch64/illegal-sysreg-7.s: New test.
+       * testsuite/gas/aarch64/sysreg-7.d: New test.
+       * testsuite/gas/aarch64/sysreg-7.s: New test.
+
 2021-03-12  Clément Chigot  <clement.chigot@atos.net>
 
        * config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section,

diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.d b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
new file mode 100644 (file)
index 0000000..d7a11ed
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d
@@ -0,0 +1,2 @@
+#source: illegal-sysreg-7.s
+#warning_output: illegal-sysreg-7.l

diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.l b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
new file mode 100644 (file)
index 0000000..1db54b3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_vtr_el2,x0'

diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.s b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
new file mode 100644 (file)
index 0000000..311e182
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s
@@ -0,0 +1,2 @@
+/* Write to R/O system registers.  */
+msr ich_vtr_el2, x0

diff --git a/gas/testsuite/gas/aarch64/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg-7.d
new file mode 100644 (file)
index 0000000..1564f53
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-7.d
@@ -0,0 +1,25 @@
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+
+.*:    d538a460        mrs     x0, lorc_el1
+.*:    d538a420        mrs     x0, lorea_el1
+.*:    d538a440        mrs     x0, lorn_el1
+.*:    d538a400        mrs     x0, lorsa_el1
+.*:    d53ecc80        mrs     x0, icc_ctlr_el3
+.*:    d538cca0        mrs     x0, icc_sre_el1
+.*:    d53cc9a0        mrs     x0, icc_sre_el2
+.*:    d53ecca0        mrs     x0, icc_sre_el3
+.*:    d53ccb20        mrs     x0, ich_vtr_el2
+.*:    d518a460        msr     lorc_el1, x0
+.*:    d518a420        msr     lorea_el1, x0
+.*:    d518a440        msr     lorn_el1, x0
+.*:    d518a400        msr     lorsa_el1, x0
+.*:    d51ecc80        msr     icc_ctlr_el3, x0
+.*:    d518cca0        msr     icc_sre_el1, x0
+.*:    d51cc9a0        msr     icc_sre_el2, x0
+.*:    d51ecca0        msr     icc_sre_el3, x0

diff --git a/gas/testsuite/gas/aarch64/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg-7.s
new file mode 100644 (file)
index 0000000..3d438d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-7.s
@@ -0,0 +1,20 @@
+/* Read from system registers.  */
+mrs x0, lorc_el1
+mrs x0, lorea_el1
+mrs x0, lorn_el1
+mrs x0, lorsa_el1
+mrs x0, icc_ctlr_el3
+mrs x0, icc_sre_el1
+mrs x0, icc_sre_el2
+mrs x0, icc_sre_el3
+mrs x0, ich_vtr_el2
+
+/* Write to system registers.  */
+msr lorc_el1, x0
+msr lorea_el1, x0
+msr lorn_el1, x0
+msr lorsa_el1, x0
+msr icc_ctlr_el3, x0
+msr icc_sre_el1, x0
+msr icc_sre_el2, x0
+msr icc_sre_el3, x0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 893a97548e5fe9d411a505476a6e0de35438833d..b3390e30bad5cc4305210a5e368d19198656c713 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
+       icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
+
 2021-03-12  Alan Modra  <amodra@gmail.com>
 
        * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 50d641239364b2d042b181b08c42a4a913c26572..521ec6f9c82d55d00c76dc972dfcf1d9d8829d94 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4570,6 +4570,16 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE ("csrptr_el2",    CPENC (2,4,C8,C0,1),  0),
   SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3),  F_REG_READ),
 
+  SR_CORE ("lorc_el1",      CPENC (3,0,C10,C4,3),  0),
+  SR_CORE ("lorea_el1",     CPENC (3,0,C10,C4,1),  0),
+  SR_CORE ("lorn_el1",      CPENC (3,0,C10,C4,2),  0),
+  SR_CORE ("lorsa_el1",     CPENC (3,0,C10,C4,0),  0),
+  SR_CORE ("icc_ctlr_el3",  CPENC (3,6,C12,C12,4), 0),
+  SR_CORE ("icc_sre_el1",   CPENC (3,0,C12,C12,5), 0),
+  SR_CORE ("icc_sre_el2",   CPENC (3,4,C12,C9,5),  0),
+  SR_CORE ("icc_sre_el3",   CPENC (3,6,C12,C12,5), 0),
+  SR_CORE ("ich_vtr_el2",   CPENC (3,4,C12,C11,1), F_REG_READ),
+
   SR_CORE ("brbcr_el1",     CPENC (2,1,C9,C0,0),  0),
   SR_CORE ("brbcr_el12",    CPENC (2,5,C9,C0,0),  0),
   SR_CORE ("brbfcr_el1",    CPENC (2,1,C9,C0,1),  0),