write_verilog: correctly map RTLIL `sync init`.

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f9207f987efd7f9324727d405ce90218acb..922b4c44c2b5eb80d83f4c9e6ab43bc38e3101b7 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 
                if (sync->type == RTLIL::STa) {
                        f << stringf("%s" "always @* begin\n", indent.c_str());
+               } else if (sync->type == RTLIL::STi) {
+                       f << stringf("%s" "initial begin\n", indent.c_str());
                } else {
                        f << stringf("%s" "always @(", indent.c_str());
                        if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1)