(no commit message)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 170f44e5f99c0fd0447b08102f813022bf480043..b239001b2e9f3b45bc3b0e34ebb04e2b5ca51568 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -27,96 +27,10 @@ Notes:
 * Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
 * Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations.  See [[sv/cr_int_predication]].
 
-# sbfm
+# Mask-suited Bitmanipulation
 
-   sbfm RT, RA, RB!=0
-
-Example
-
-     7 6 5 4 3 2 1 0   Bit index
-
-     1 0 0 1 0 1 0 0   v3 contents
-                       vmsbf.m v2, v3
-     0 0 0 0 0 0 1 1   v2 contents
-
-     1 0 0 1 0 1 0 1   v3 contents
-                       vmsbf.m v2, v3
-     0 0 0 0 0 0 0 0   v2
-
-     0 0 0 0 0 0 0 0   v3 contents
-                       vmsbf.m v2, v3
-     1 1 1 1 1 1 1 1   v2
-
-     1 1 0 0 0 0 1 1   RB vcontents
-     1 0 0 1 0 1 0 0   v3 contents
-                       vmsbf.m v2, v3, v0.t
-     0 1 x x x x 1 1   v2 contents
-
-The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1.
-
-Executable pseudocode demo:
-
-```
-[[!inline quick="yes" raw="yes" pages="openpower/sv/sbf.py"]]
-```
-
-# sifm
-
-The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.
-
-    sifm RT, RA, RB!=0
-
- # Example
-
-     7 6 5 4 3 2 1 0   Bit number
-
-     1 0 0 1 0 1 0 0   v3 contents
-                       vmsif.m v2, v3
-     0 0 0 0 0 1 1 1   v2 contents
-
-     1 0 0 1 0 1 0 1   v3 contents
-                       vmsif.m v2, v3
-     0 0 0 0 0 0 0 1   v2
-
-     1 1 0 0 0 0 1 1   RB vcontents
-     1 0 0 1 0 1 0 0   v3 contents
-                       vmsif.m v2, v3, v0.t
-     1 1 x x x x 1 1   v2 contents
-
-Executable pseudocode demo:
-
-```
-[[!inline quick="yes" raw="yes" pages="openpower/sv/sif.py"]]
-```
-
-# vmsof
-
-The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.
-
-    sofm RT, RA, RB
-
-Example
-
-     7 6 5 4 3 2 1 0   Bit number
-
-     1 0 0 1 0 1 0 0   v3 contents
-                       vmsof.m v2, v3
-     0 0 0 0 0 1 0 0   v2 contents
-
-     1 0 0 1 0 1 0 1   v3 contents
-                       vmsof.m v2, v3
-     0 0 0 0 0 0 0 1   v2
-
-     1 1 0 0 0 0 1 1   RB vcontents
-     1 1 0 1 0 1 0 0   v3 contents
-                       vmsof.m v2, v3, v0.t
-     0 1 x x x x 0 0   v2 content
-
-Executable pseudocode demo:
-
-```
-[[!inline quick="yes" raw="yes" pages="openpower/sv/sof.py"]]
-```
+UNDER DEVELOPMENT, sbf/sof/sif moved to [[discussion] and
+general-purpose replacements being designed
 
 # Carry-lookahead