gallium/radeon: rename r600_context_bo_reloc -> radeon_add_to_buffer_list

this name should be easy to understand without other knowledge

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index ede9a1b3edc1a2138d8b2e290b0105ddabba1fd9..33009c16f688985005bb4b13f93715a41215ccd2 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -439,7 +439,7 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
        /* XXX support more than 8 colorbuffers (the offsets are not a multiple of 0x3C for CB8-11) */
        for (i = 0; i < 8 && i < ctx->framebuffer.state.nr_cbufs; i++) {
                struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i];
-               unsigned reloc = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx,
+               unsigned reloc = radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.gfx,
                                                       (struct r600_resource*)cb->base.texture,
                                                       RADEON_USAGE_READWRITE,
                                                       RADEON_PRIO_SHADER_RESOURCE_RW);
@@ -564,7 +564,7 @@ void evergreen_emit_cs_shader(
        radeon_emit(cs, 0);     /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
 
        radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
-       radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+       radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                              code_bo, RADEON_USAGE_READ,
                                              RADEON_PRIO_SHADER_DATA));
 }

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index e2728565489993165926c378adafb0267e634d0d..29bdd9daddb47441d3e45eedc6db51e27098fab5 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -64,9 +64,9 @@ void evergreen_dma_copy_buffer(struct r600_context *rctx,
        for (i = 0; i < ncopy; i++) {
                csize = size < EG_DMA_COPY_MAX_SIZE ? size : EG_DMA_COPY_MAX_SIZE;
                /* emit reloc before writing cs so that cs is always in consistent state */
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
                                      RADEON_PRIO_MIN);
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
                                      RADEON_PRIO_MIN);
                cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize);
                cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
@@ -129,7 +129,7 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
                }
 
                /* This must be done after r600_need_cs_space. */
-               reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+               reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                              (struct r600_resource*)dst, RADEON_USAGE_WRITE,
                                              RADEON_PRIO_MIN);
 

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 5c03f0e6c4425cb84c84034786478841147d183f..9ef92741879771bc5bd7b30ef1332ac3fa557cf2 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1562,7 +1562,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
                }
 
                tex = (struct r600_texture *)cb->base.texture;
-               reloc = r600_context_bo_reloc(&rctx->b,
+               reloc = radeon_add_to_buffer_list(&rctx->b,
                                              &rctx->b.rings.gfx,
                                              (struct r600_resource*)cb->base.texture,
                                              RADEON_USAGE_READWRITE,
@@ -1571,7 +1571,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
                                                      RADEON_PRIO_COLOR_BUFFER);
 
                if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
-                       cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+                       cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                tex->cmask_buffer, RADEON_USAGE_READWRITE,
                                RADEON_PRIO_COLOR_META);
                } else {
@@ -1616,7 +1616,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
                                       cb->cb_color_info | tex->cb_color_info);
 
                if (!rctx->keep_tiling_flags) {
-                       unsigned reloc = r600_context_bo_reloc(&rctx->b,
+                       unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
                                                               &rctx->b.rings.gfx,
                                                               (struct r600_resource*)state->cbufs[0]->texture,
                                                               RADEON_USAGE_READWRITE,
@@ -1639,7 +1639,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
        /* ZS buffer. */
        if (state->zsbuf) {
                struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
-               unsigned reloc = r600_context_bo_reloc(&rctx->b,
+               unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
                                                       &rctx->b.rings.gfx,
                                                       (struct r600_resource*)state->zsbuf->texture,
                                                       RADEON_USAGE_READWRITE,
@@ -1755,7 +1755,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom
                radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
                radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
                radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
-               reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
+               reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
                                                  RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
                cs->buf[cs->cdw++] = reloc_idx;
@@ -1869,7 +1869,7 @@ static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
                radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
 
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
        }
        state->dirty_mask = 0;
@@ -1917,7 +1917,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
                }
 
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
 
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
@@ -1942,7 +1942,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
                            S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
 
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
 
                dirty_mask &= ~(1 << buffer_index);
@@ -2001,7 +2001,7 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx,
                radeon_emit(cs, (resource_id_base + resource_index) * 8);
                radeon_emit_array(cs, rview->tex_resource_words, 8);
 
-               reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
+               reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
                                              RADEON_USAGE_READ,
                                              rview->tex_resource->b.b.nr_samples > 1 ?
                                                      RADEON_PRIO_SHADER_TEXTURE_MSAA :
@@ -2124,7 +2124,7 @@ static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct
        radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
                               (shader->buffer->gpu_address + shader->offset) >> 8);
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-       radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
+       radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
                                              RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
 }
 
@@ -2182,7 +2182,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
                radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
                                rbuffer->gpu_address >> 8);
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
                                                      RADEON_PRIO_SHADER_RESOURCE_RW));
                radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
@@ -2192,7 +2192,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom
                radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
                                rbuffer->gpu_address >> 8);
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
                                                      RADEON_PRIO_SHADER_RESOURCE_RW));
                radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
@@ -3307,9 +3307,9 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
                }
                size = (cheight * pitch) / 4;
                /* emit reloc before writing cs so that cs is always in consistent state */
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, &rsrc->resource,
                                      RADEON_USAGE_READ, RADEON_PRIO_MIN);
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, &rdst->resource,
                                      RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
                cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
                cs->buf[cs->cdw++] = base >> 8;

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index d5eec15f1fbd2aa150070ac527428c5829779686..2fe29e91c4f2d7b2954923df04a285b54eb86b5d 100644 (file)
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -417,9 +417,9 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
                }
 
                /* This must be done after r600_need_cs_space. */
-               src_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src,
+               src_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src,
                                                  RADEON_USAGE_READ, RADEON_PRIO_MIN);
-               dst_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst,
+               dst_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst,
                                                  RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
 
                radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
@@ -470,9 +470,9 @@ void r600_dma_copy_buffer(struct r600_context *rctx,
        for (i = 0; i < ncopy; i++) {
                csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
                /* emit reloc before writing cs so that cs is always in consistent state */
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
                                      RADEON_PRIO_MIN);
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
                                      RADEON_PRIO_MIN);
                cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize);
                cs->buf[cs->cdw++] = dst_offset & 0xfffffffc;

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 1af96f64d40ec866fca5e5510676db90d07a601f..aff8f03f9b11765a89d4830bca5fc3cff1c58a41 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1410,7 +1410,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
                        /* COLOR_BASE */
                        radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
 
-                       reloc = r600_context_bo_reloc(&rctx->b,
+                       reloc = radeon_add_to_buffer_list(&rctx->b,
                                                      &rctx->b.rings.gfx,
                                                      (struct r600_resource*)cb[i]->base.texture,
                                                      RADEON_USAGE_READWRITE,
@@ -1423,7 +1423,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
                        /* FMASK */
                        radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
 
-                       reloc = r600_context_bo_reloc(&rctx->b,
+                       reloc = radeon_add_to_buffer_list(&rctx->b,
                                                      &rctx->b.rings.gfx,
                                                      cb[i]->cb_buffer_fmask,
                                                      RADEON_USAGE_READWRITE,
@@ -1436,7 +1436,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
                        /* CMASK */
                        radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
 
-                       reloc = r600_context_bo_reloc(&rctx->b,
+                       reloc = radeon_add_to_buffer_list(&rctx->b,
                                                      &rctx->b.rings.gfx,
                                                      cb[i]->cb_buffer_cmask,
                                                      RADEON_USAGE_READWRITE,
@@ -1475,7 +1475,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
        /* Zbuffer. */
        if (state->zsbuf) {
                struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
-               unsigned reloc = r600_context_bo_reloc(&rctx->b,
+               unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
                                                       &rctx->b.rings.gfx,
                                                       (struct r600_resource*)state->zsbuf->texture,
                                                       RADEON_USAGE_READWRITE,
@@ -1589,7 +1589,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom
                radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
                radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
                radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
-               reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
+               reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
                                                  RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
                cs->buf[cs->cdw++] = reloc_idx;
@@ -1704,7 +1704,7 @@ static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom
                radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
 
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
        }
 }
@@ -1737,7 +1737,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
                }
 
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
 
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
@@ -1753,7 +1753,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
                radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
 
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
 
                dirty_mask &= ~(1 << buffer_index);
@@ -1801,7 +1801,7 @@ static void r600_emit_sampler_views(struct r600_context *rctx,
                radeon_emit(cs, (resource_id_base + resource_index) * 7);
                radeon_emit_array(cs, rview->tex_resource_words, 7);
 
-               reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
+               reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
                                              RADEON_USAGE_READ,
                                              rview->tex_resource->b.b.nr_samples > 1 ?
                                                      RADEON_PRIO_SHADER_TEXTURE_MSAA :
@@ -1932,7 +1932,7 @@ static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600
 
        radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-       radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
+       radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
                                              RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
 }
 
@@ -1985,7 +1985,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
                rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
                radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
                                                      RADEON_PRIO_SHADER_RESOURCE_RW));
                radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
@@ -1994,7 +1994,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
                rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
                radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-               radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+               radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
                                                      RADEON_PRIO_SHADER_RESOURCE_RW));
                radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
@@ -2901,9 +2901,9 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
                cheight = cheight > copy_height ? copy_height : cheight;
                size = (cheight * pitch) / 4;
                /* emit reloc before writing cs so that cs is always in consistent state */
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
                                      RADEON_PRIO_MIN);
-               r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
+               radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
                                      RADEON_PRIO_MIN);
                cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
                cs->buf[cs->cdw++] = base >> 8;

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 9f6884d21095281885c774b45e23173ff8933e2f..24ed74b40d697844b434304aebc284f4961870e8 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1620,7 +1620,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
 
                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
-               cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+               cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                                           (struct r600_resource*)info.indirect,
                                                           RADEON_USAGE_READ, RADEON_PRIO_MIN);
        }
@@ -1649,7 +1649,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                                cs->buf[cs->cdw++] = info.count;
                                cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
                                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
-                               cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+                               cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                                                           (struct r600_resource*)ib.buffer,
                                                                           RADEON_USAGE_READ, RADEON_PRIO_MIN);
                        }
@@ -1661,7 +1661,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                                cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
 
                                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
-                               cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+                               cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                                                           (struct r600_resource*)ib.buffer,
                                                                           RADEON_USAGE_READ, RADEON_PRIO_MIN);
 
@@ -1688,7 +1688,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                        cs->buf[cs->cdw++] = 0; /* unused */
 
                        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
-                       cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+                       cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
                                                                   t->buf_filled_size, RADEON_USAGE_READ,
                                                                   RADEON_PRIO_MIN);
                }
@@ -1879,7 +1879,7 @@ void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
 
        r600_emit_command_buffer(cs, &shader->command_buffer);
        radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-       radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
+       radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, shader->bo,
                                              RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
 }
 
@@ -2607,7 +2607,7 @@ void r600_trace_emit(struct r600_context *rctx)
        uint32_t reloc;
 
        va = rscreen->b.trace_bo->gpu_address;
-       reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
+       reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
                                      RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
        radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
        radeon_emit(cs, va & 0xFFFFFFFFUL);

diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h
index 188abccb507274cfc15a8d87038e8eb65a91e78f..fa40dc42a31b517676893b1d2b30ce407e666532 100644 (file)
--- a/src/gallium/drivers/radeon/r600_cs.h
+++ b/src/gallium/drivers/radeon/r600_cs.h
@@ -33,11 +33,21 @@
 #include "r600_pipe_common.h"
 #include "r600d_common.h"
 
-static inline unsigned r600_context_bo_reloc(struct r600_common_context *rctx,
-                                            struct r600_ring *ring,
-                                            struct r600_resource *rbo,
-                                            enum radeon_bo_usage usage,
-                                            enum radeon_bo_priority priority)
+/**
+ * Add a buffer to the buffer list for the given command stream (CS).
+ *
+ * All buffers used by a CS must be added to the list. This tells the kernel
+ * driver which buffers are used by GPU commands. Other buffers can
+ * be swapped out (not accessible) during execution.
+ *
+ * The buffer list becomes empty after every context flush and must be
+ * rebuilt.
+ */
+static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
+                                                struct r600_ring *ring,
+                                                struct r600_resource *rbo,
+                                                enum radeon_bo_usage usage,
+                                                enum radeon_bo_priority priority)
 {
        assert(usage);
 
@@ -66,7 +76,7 @@ static inline void r600_emit_reloc(struct r600_common_context *rctx,
 {
        struct radeon_winsys_cs *cs = ring->cs;
        bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_virtual_address;
-       unsigned reloc = r600_context_bo_reloc(rctx, ring, rbo, usage, priority);
+       unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
 
        if (!has_vm) {
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 47b586f171e3b265503cb80fff28c69b2913c38d..8b0ce9f1bb8c4ef91bfd106ac13e827e7d691d2c 100644 (file)
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -61,9 +61,9 @@ static void cik_sdma_do_copy_buffer(struct si_context *ctx,
        ncopy = (size + CIK_SDMA_COPY_MAX_SIZE - 1) / CIK_SDMA_COPY_MAX_SIZE;
        r600_need_dma_space(&ctx->b, ncopy * 7);
 
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
                              RADEON_PRIO_MIN);
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
                              RADEON_PRIO_MIN);
 
        for (i = 0; i < ncopy; i++) {
@@ -171,9 +171,9 @@ static void cik_sdma_copy_tile(struct si_context *ctx,
        ncopy = (copy_height + cheight - 1) / cheight;
        r600_need_dma_space(&ctx->b, ncopy * 12);
 
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
                              RADEON_USAGE_READ, RADEON_PRIO_MIN);
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
                              RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
 
        copy_height = size * 4 / pitch;

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 8dd12f63e633f6a130b59f4c6d19dd96ea93ec17..7b8a8433cc6bd1428f1c7f3bf649e9be5c2eb7dd 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -159,7 +159,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
                                 FALSE);
 
                /* This must be done after need_cs_space. */
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource*)dst, RADEON_USAGE_WRITE,
                                      RADEON_PRIO_MIN);
 
@@ -240,9 +240,9 @@ void si_copy_buffer(struct si_context *sctx,
                }
 
                /* This must be done after r600_need_cs_space. */
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src,
                                      RADEON_USAGE_READ, RADEON_PRIO_MIN);
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst,
                                      RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
 
                si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags);

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 558814352aa6247dd0a81cedd8d3e20e5d31db1c..762a4b77e5dd3bfb503f96d35d01bb1e7c320a68 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -117,7 +117,7 @@ static bool si_upload_descriptors(struct si_context *sctx,
 
        util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
 
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, desc->buffer,
                              RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
 
        desc->list_dirty = false;
@@ -163,14 +163,14 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx,
                if (!rview->resource)
                        continue;
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      rview->resource, RADEON_USAGE_READ,
                                      si_get_resource_ro_priority(rview->resource));
        }
 
        if (!views->desc.buffer)
                return;
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer,
                              RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
 }
 
@@ -188,7 +188,7 @@ static void si_set_sampler_view(struct si_context *sctx, unsigned shader,
                        (struct si_sampler_view*)view;
 
                if (rview->resource)
-                       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                rview->resource, RADEON_USAGE_READ,
                                si_get_resource_ro_priority(rview->resource));
 
@@ -269,7 +269,7 @@ static void si_sampler_states_begin_new_cs(struct si_context *sctx,
 {
        if (!states->desc.buffer)
                return;
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, states->desc.buffer,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, states->desc.buffer,
                              RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_DATA);
 }
 
@@ -335,14 +335,14 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
        while (mask) {
                int i = u_bit_scan64(&mask);
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource*)buffers->buffers[i],
                                      buffers->shader_usage, buffers->priority);
        }
 
        if (!buffers->desc.buffer)
                return;
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                              buffers->desc.buffer, RADEON_USAGE_READWRITE,
                              RADEON_PRIO_SHADER_DATA);
 }
@@ -363,14 +363,14 @@ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
                if (!sctx->vertex_buffer[vb].buffer)
                        continue;
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
                                      RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO);
        }
 
        if (!desc->buffer)
                return;
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                              desc->buffer, RADEON_USAGE_READ,
                              RADEON_PRIO_SHADER_DATA);
 }
@@ -397,7 +397,7 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
        if (!desc->buffer)
                return false;
 
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                              desc->buffer, RADEON_USAGE_READ,
                              RADEON_PRIO_SHADER_DATA);
 
@@ -441,7 +441,7 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
                desc[3] = sctx->vertex_elements->rsrc_word3[i];
 
                if (!bound[ve->vertex_buffer_index]) {
-                       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                              (struct r600_resource*)vb->buffer,
                                              RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO);
                        bound[ve->vertex_buffer_index] = true;
@@ -520,7 +520,7 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint s
                          S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 
                buffers->buffers[slot] = buffer;
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource*)buffer,
                                      buffers->shader_usage, buffers->priority);
                buffers->desc.enabled_mask |= 1llu << slot;
@@ -615,7 +615,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
                          S_008F0C_ADD_TID_ENABLE(add_tid);
 
                pipe_resource_reference(&buffers->buffers[slot], buffer);
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource*)buffer,
                                      buffers->shader_usage, buffers->priority);
                buffers->desc.enabled_mask |= 1llu << slot;
@@ -705,7 +705,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                        /* Set the resource. */
                        pipe_resource_reference(&buffers->buffers[bufidx],
                                                buffer);
-                       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                              (struct r600_resource*)buffer,
                                              buffers->shader_usage, buffers->priority);
                        buffers->desc.enabled_mask |= 1llu << bufidx;
@@ -804,7 +804,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
                                                            old_va, buf);
                                buffers->desc.list_dirty = true;
 
-                               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                                      rbuffer, buffers->shader_usage,
                                                      buffers->priority);
 
@@ -833,7 +833,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
                                                            old_va, buf);
                                buffers->desc.list_dirty = true;
 
-                               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                                      rbuffer, buffers->shader_usage,
                                                      buffers->priority);
                        }
@@ -858,7 +858,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
                                                            old_va, buf);
                                views->desc.list_dirty = true;
 
-                               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                                      rbuffer, RADEON_USAGE_READ,
                                                      RADEON_PRIO_SHADER_BUFFER_RO);
                        }

diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index 1a7eeaecf9e561f837c796d7690308c6d803c0d9..309ae04424a652638676e1cf0eafa3ace45a6027 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -78,9 +78,9 @@ static void si_dma_copy_buffer(struct si_context *ctx,
 
        r600_need_dma_space(&ctx->b, ncopy * 5);
 
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
                              RADEON_PRIO_MIN);
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
                              RADEON_PRIO_MIN);
 
        for (i = 0; i < ncopy; i++) {
@@ -177,9 +177,9 @@ static void si_dma_copy_tile(struct si_context *ctx,
        ncopy = (size / SI_DMA_COPY_MAX_SIZE_DW) + !!(size % SI_DMA_COPY_MAX_SIZE_DW);
        r600_need_dma_space(&ctx->b, ncopy * 9);
 
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
                              RADEON_USAGE_READ, RADEON_PRIO_MIN);
-       r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
+       radeon_add_to_buffer_list(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
                              RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
 
        for (i = 0; i < ncopy; i++) {

diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c
index 036d90cabb10bbe34c1b6255bcf8ebba52c7b685..9c4d7ec8ba3809c38acd7d4bfa69f57cbce88100 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -144,7 +144,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
 {
        struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
        for (int i = 0; i < state->nbo; ++i) {
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
                                      state->bo_usage[i], state->bo_priority[i]);
        }
 

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 5c922b04c0a00203642e3e1117a79588fb13c2c9..dd0fe0e2edf84f1264985b583a6db3e9535b0379 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2235,14 +2235,14 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
                }
 
                tex = (struct r600_texture *)cb->base.texture;
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      &tex->resource, RADEON_USAGE_READWRITE,
                                      tex->surface.nsamples > 1 ?
                                              RADEON_PRIO_COLOR_BUFFER_MSAA :
                                              RADEON_PRIO_COLOR_BUFFER);
 
                if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
-                       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                tex->cmask_buffer, RADEON_USAGE_READWRITE,
                                RADEON_PRIO_COLOR_META);
                }
@@ -2282,14 +2282,14 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
                struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
                struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      &rtex->resource, RADEON_USAGE_READWRITE,
                                      zb->base.texture->nr_samples > 1 ?
                                              RADEON_PRIO_DEPTH_BUFFER_MSAA :
                                              RADEON_PRIO_DEPTH_BUFFER);
 
                if (zb->db_htile_data_base) {
-                       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+                       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                              rtex->htile_buffer, RADEON_USAGE_READWRITE,
                                              RADEON_PRIO_DEPTH_META);
                }

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index ebcc26917734e8362689f118749961b52d133247..36f15852843365c051c85ac858107782b85b5163 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -351,7 +351,7 @@ static void si_emit_scratch_reloc(struct si_context *sctx)
                               sctx->spi_tmpring_size);
 
        if (sctx->scratch_buffer) {
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      sctx->scratch_buffer, RADEON_USAGE_READWRITE,
                                      RADEON_PRIO_SHADER_RESOURCE_RW);
 
@@ -465,7 +465,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
                radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
                radeon_emit(cs, 0); /* unused */
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      t->buf_filled_size, RADEON_USAGE_READ,
                                      RADEON_PRIO_MIN);
        }
@@ -519,7 +519,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
        } else {
                si_invalidate_draw_sh_constants(sctx);
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource *)info->indirect,
                                      RADEON_USAGE_READ, RADEON_PRIO_MIN);
        }
@@ -529,7 +529,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
                                          ib->index_size;
                uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
 
-               r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
                                      (struct r600_resource *)ib->buffer,
                                      RADEON_USAGE_READ, RADEON_PRIO_MIN);
 
@@ -876,7 +876,7 @@ void si_trace_emit(struct si_context *sctx)
        struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
 
        sctx->trace_id++;
-       r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sctx->trace_buf,
+       radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, sctx->trace_buf,
                              RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
        radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |