#define R600_IT_ME_INITIALIZE 0x00004400
#define R600_IT_COND_WRITE 0x00004500
#define R600_IT_EVENT_WRITE 0x00004600
+# define R600_EVENT_TYPE(x) ((x) << 0)
+# define R600_EVENT_INDEX(x) ((x) << 8)
#define R600_IT_EVENT_WRITE_EOP 0x00004700
#define R600_IT_ONE_REG_WRITE 0x00005700
#define R600_IT_SET_CONFIG_REG 0x00006800
BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(ZPASS_DONE);
+ R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
R600_OUT_BATCH(0x00000000);
R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
- R600_OUT_BATCH(ZPASS_DONE);
+ R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
R600_OUT_BATCH(0x00000000);
R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);