radv: for stencil only set Z tile mode index to same value

On SI this was causing a hang in
dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint

This was due to not handling the tile mode index for depth like
I fixed previously for new GPUs.

Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 752d70be4bb374b7a0aef3e51a92f1adcc5116df..eb2587212c8ca69a7ac19047e3edd6347adff9d0 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3246,6 +3246,8 @@ radv_initialise_ds_surface(struct radv_device *device,
                        ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
                        tile_mode_index = si_tile_mode_index(iview->image, level, true);
                        ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
+                       if (stencil_only)
+                               ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
                }
 
                ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |