cpp = 1;
break;
case VC4_TEXTURE_TYPE_ETC1:
+ /* ETC1 is arranged as 64-bit blocks, where each block is 4x4
+ * pixels.
+ */
+ cpp = 8;
+ width = (width + 3) >> 2;
+ height = (height + 3) >> 2;
+ break;
case VC4_TEXTURE_TYPE_BW1:
case VC4_TEXTURE_TYPE_A4:
case VC4_TEXTURE_TYPE_A1:
FORMAT(B5G6R5_UNORM, RGB565, RGB565, SWIZ(X, Y, Z, 1)),
+ FORMAT(ETC1_RGB8, NO, ETC1, SWIZ(X, Y, Z, 1)),
+
/* Depth sampling will be handled by doing nearest filtering and not
* unpacking the RGBA value.
*/
if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
return NULL;
+ if (format == PIPE_FORMAT_ETC1_RGB8) {
+ /* ETC1 is arranged as 64-bit blocks, where each block
+ * is 4x4 pixels. Texture tiling operates on the
+ * 64-bit block the way it would an uncompressed
+ * pixels.
+ */
+ assert(!(ptrans->box.x & 3));
+ assert(!(ptrans->box.y & 3));
+ ptrans->box.x >>= 2;
+ ptrans->box.y >>= 2;
+ ptrans->box.width = (ptrans->box.width + 3) >> 2;
+ ptrans->box.height = (ptrans->box.height + 3) >> 2;
+ }
+
/* We need to align the box to utile boundaries, since that's
* what load/store operates on. This may cause us to need to
* read out the original contents in that border area. Right
struct pipe_resource *prsc = &rsc->base.b;
uint32_t width = prsc->width0;
uint32_t height = prsc->height0;
+ if (prsc->format == PIPE_FORMAT_ETC1_RGB8) {
+ width = (width + 3) >> 2;
+ height = (height + 3) >> 2;
+ }
+
uint32_t pot_width = util_next_power_of_two(width);
uint32_t pot_height = util_next_power_of_two(height);
uint32_t offset = 0;
}
if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
- vc4_tex_format_supported(format)) {
+ vc4_tex_format_supported(format) &&
+ format != PIPE_FORMAT_ETC1_RGB8) {
retval |= PIPE_BIND_SAMPLER_VIEW;
}
VC4_SET_FIELD(prsc->height0 & 2047, VC4_TEX_P1_HEIGHT) |
VC4_SET_FIELD(prsc->width0 & 2047, VC4_TEX_P1_WIDTH));
+ if (prsc->format == PIPE_FORMAT_ETC1_RGB8)
+ so->texture_p1 |= VC4_TEX_P1_ETCFLIP_MASK;
+
return &so->base;
}