gallium/radeon: clean up r600_query_init_backend_mask

This just needs to be done for r600g in the screen.
We don't need an IB submission for every new context created for GCN.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index d48c56635feb315695c3ad75bbb728d683ed21a7..1d9111d004b3fb3c8cc08e6957956f1f653b5f5a 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -207,7 +207,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen,
        rctx->blitter->draw_rectangle = r600_draw_rectangle;
 
        r600_begin_new_cs(rctx);
-       r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 
        rctx->dummy_pixel_shader =
                util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
@@ -736,5 +735,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        if (rscreen->b.debug_flags & DBG_TEST_DMA)
                r600_test_dma(&rscreen->b);
 
+       r600_query_fix_enabled_rb_mask(rscreen);
        return &rscreen->b.b;
 }

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 7c8fe786156fdd438f6474f1574b6c7bcd5bbad9..9adb8ec53da52ed3678e2dfee84dea858ff1576a 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1308,6 +1308,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
                printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
                printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
                printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
+               printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
        }
        return true;
 }

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index afb1385f97e72470209c4373351da1a7c384f7be..e72f4a2a649992f2542260c2b14b70424a19164e 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -586,7 +586,6 @@ struct r600_common_context {
        struct list_head                active_queries;
        unsigned                        num_cs_dw_queries_suspend;
        /* Additional hardware info. */
-       unsigned                        backend_mask;
        unsigned                        max_db; /* for OQ */
        /* Misc stats. */
        unsigned                        num_draw_calls;
@@ -775,7 +774,7 @@ void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 void r600_query_init(struct r600_common_context *rctx);
 void r600_suspend_queries(struct r600_common_context *ctx);
 void r600_resume_queries(struct r600_common_context *ctx);
-void r600_query_init_backend_mask(struct r600_common_context *ctx);
+void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
 
 /* r600_streamout.c */
 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);

diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index d4e41306a443b2251f771ed680f147a154da7d47..cf5e62115b64799706c2fd9e400e771d82a758c5 100644 (file)
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -435,6 +435,7 @@ static bool r600_query_hw_prepare_buffer(struct r600_common_context *ctx,
 
        if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
            query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
+               unsigned enabled_rb_mask = ctx->screen->info.enabled_rb_mask;
                unsigned num_results;
                unsigned i, j;
 
@@ -442,7 +443,7 @@ static bool r600_query_hw_prepare_buffer(struct r600_common_context *ctx,
                num_results = buffer->b.b.width0 / query->result_size;
                for (j = 0; j < num_results; j++) {
                        for (i = 0; i < ctx->max_db; i++) {
-                               if (!(ctx->backend_mask & (1<<i))) {
+                               if (!(enabled_rb_mask & (1<<i))) {
                                        results[(i * 4)+1] = 0x80000000;
                                        results[(i * 4)+3] = 0x80000000;
                                }
@@ -1611,19 +1612,22 @@ void r600_resume_queries(struct r600_common_context *ctx)
        }
 }
 
-/* Get backends mask */
-void r600_query_init_backend_mask(struct r600_common_context *ctx)
+/* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
+void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
 {
+       struct r600_common_context *ctx =
+               (struct r600_common_context*)rscreen->aux_context;
        struct radeon_winsys_cs *cs = ctx->gfx.cs;
        struct r600_resource *buffer;
        uint32_t *results;
-       unsigned num_backends = ctx->screen->info.num_render_backends;
        unsigned i, mask = 0;
 
+       assert(rscreen->chip_class <= CAYMAN);
+
        /* if backend_map query is supported by the kernel */
-       if (ctx->screen->info.r600_gb_backend_map_valid) {
-               unsigned num_tile_pipes = ctx->screen->info.num_tile_pipes;
-               unsigned backend_map = ctx->screen->info.r600_gb_backend_map;
+       if (rscreen->info.r600_gb_backend_map_valid) {
+               unsigned num_tile_pipes = rscreen->info.num_tile_pipes;
+               unsigned backend_map = rscreen->info.r600_gb_backend_map;
                unsigned item_width, item_mask;
 
                if (ctx->chip_class >= EVERGREEN) {
@@ -1640,7 +1644,7 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
                        backend_map >>= item_width;
                }
                if (mask != 0) {
-                       ctx->backend_mask = mask;
+                       rscreen->info.enabled_rb_mask = mask;
                        return;
                }
        }
@@ -1652,7 +1656,7 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
                pipe_buffer_create(ctx->b.screen, 0,
                                   PIPE_USAGE_STAGING, ctx->max_db*16);
        if (!buffer)
-               goto err;
+               return;
 
        /* initialize buffer with zeroes */
        results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
@@ -1681,15 +1685,8 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
 
        r600_resource_reference(&buffer, NULL);
 
-       if (mask != 0) {
-               ctx->backend_mask = mask;
-               return;
-       }
-
-err:
-       /* fallback to old method - set num_backends lower bits to 1 */
-       ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
-       return;
+       if (mask)
+               rscreen->info.enabled_rb_mask = mask;
 }
 
 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index d4d156b8a69a07d70939b2ffffe7744331c85d88..0bd82ebe853aa4b69b719c5b893e179f00dc436a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -253,7 +253,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 
        /* these must be last */
        si_begin_new_cs(sctx);
-       r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 
        /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
         * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3a92b588eb2e14f5d12aa242d7ac509125fcf923..278d4f317e83db43706a22b56d9e26f4d6f3e0c4 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -385,6 +385,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
                          &ws->info.max_shader_clock);
     ws->info.max_shader_clock /= 1000;
 
+    /* Default value. */
+    ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
+    /* This fails on non-GCN or older kernels: */
     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
                          &ws->info.enabled_rb_mask);