This patch adds new target selectors for SVE and updates existing
selectors accordingly. It also XFAILs some tests that don't yet
work for some SVE modes; most of these go away with follow-on
vectorisation enhancements.
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_aarch64_sve)
(aarch64_sve_bits, check_effective_target_aarch64_sve_hw)
(aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw):
New procedures.
(check_effective_target_vect_perm): Handle SVE.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
(check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise.
(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
(check_effective_target_vect_element_align_preferred): Likewise.
(check_effective_target_vect_align_stack_vars): Likewise.
(check_effective_target_vect_load_lanes): Likewise.
(check_effective_target_vect_masked_store): Likewise.
(available_vector_sizes): Use aarch64_sve_bits for SVE.
* gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately
for SVE.
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL.
* gcc.dg/vect/bb-slp-pr69907.c: Likewise.
* gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise.
* gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise.
* gcc.dg/vect/slp-23.c: Likewise.
* gcc.dg/vect/slp-perm-5.c: Likewise.
* gcc.dg/vect/slp-perm-6.c: Likewise.
* gcc.dg/vect/slp-perm-9.c: Likewise.
* gcc.dg/vect/slp-reduc-3.c: Likewise.
* gcc.dg/vect/vect-114.c: Likewise.
* gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise.
* gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise.
Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256613
+2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * lib/target-supports.exp (check_effective_target_aarch64_sve)
+ (aarch64_sve_bits, check_effective_target_aarch64_sve_hw)
+ (aarch64_sve_hw_bits, check_effective_target_aarch64_sve256_hw):
+ New procedures.
+ (check_effective_target_vect_perm): Handle SVE.
+ (check_effective_target_vect_perm_byte): Likewise.
+ (check_effective_target_vect_perm_short): Likewise.
+ (check_effective_target_vect_widen_sum_hi_to_si_pattern): Likewise.
+ (check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
+ (check_effective_target_vect_widen_mult_hi_to_si): Likewise.
+ (check_effective_target_vect_element_align_preferred): Likewise.
+ (check_effective_target_vect_align_stack_vars): Likewise.
+ (check_effective_target_vect_load_lanes): Likewise.
+ (check_effective_target_vect_masked_store): Likewise.
+ (available_vector_sizes): Use aarch64_sve_bits for SVE.
+ * gcc.dg/vect/tree-vect.h (VECTOR_BITS): Define appropriately
+ for SVE.
+ * gcc.dg/tree-ssa/ssa-dom-cse-2.c: Add SVE XFAIL.
+ * gcc.dg/vect/bb-slp-pr69907.c: Likewise.
+ * gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise.
+ * gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise.
+ * gcc.dg/vect/slp-23.c: Likewise.
+ * gcc.dg/vect/slp-perm-5.c: Likewise.
+ * gcc.dg/vect/slp-perm-6.c: Likewise.
+ * gcc.dg/vect/slp-perm-9.c: Likewise.
+ * gcc.dg/vect/slp-reduc-3.c: Likewise.
+ * gcc.dg/vect/vect-114.c: Likewise.
+ * gcc.dg/vect/vect-mult-const-pattern-1.c: Likewise.
+ * gcc.dg/vect/vect-mult-const-pattern-2.c: Likewise.
+
2018-01-13 Richard Sandiford <richard.sandiford@linaro.org>
* gcc.dg/vect/no-scevccp-slp-30.c: XFAIL SLP test for
but the loop reads only one element at a time, and DOM cannot resolve these.
The same happens on powerpc depending on the SIMD support available. */
-/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* } || { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* nvptx*-*-* } || { { lp64 && { powerpc*-*-* sparc*-*-* riscv*-*-* } } || aarch64_sve } } } } } */
p1[n] = p2[n * 2];
}
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" } } */
+/* Disable for SVE because for long or variable-length vectors we don't
+ get an unrolled epilogue loop. */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64_sve } } } } */
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {xfail { vect_no_align && { ! vect_hw_misalign } } } } } */
-/* { dg-final { scan-tree-dump-times "dependence distance negative" 1 "vect" } } */
+/* Requires reverse for variable-length SVE, which is implemented for
+ by a later patch. Until then we report it twice, once for SVE and
+ once for 128-bit Advanced SIMD. */
+/* { dg-final { scan-tree-dump-times "dependence distance negative" 1 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" {xfail { vect_no_align && { ! vect_hw_misalign } } } } } */
-/* { dg-final { scan-tree-dump-times "dependence distance negative" 4 "vect" } } */
+/* f4 requires reverse for SVE, which is implemented by a later patch.
+ Until then we report it twice, once for SVE and once for 128-bit
+ Advanced SIMD. */
+/* { dg-final { scan-tree-dump-times "dependence distance negative" 4 "vect" { xfail { aarch64_sve && vect_variable_length } } } } */
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } } } } */
+/* We fail to vectorize the second loop with variable-length SVE but
+ fall back to 128-bit vectors, which does use SLP. */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_perm } xfail aarch64_sve } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_perm } } } */
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } } } } */
+/* Fails for variable-length SVE because we fall back to Advanced SIMD
+ and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target vect_load_lanes } } } */
/* { dg-final { scan-tree-dump "note: Built SLP cancelled: can use load/store-lanes" "vect" { target { vect_perm3_int && vect_load_lanes } } } } */
/* { dg-final { scan-tree-dump "LOAD_LANES" "vect" { target vect_load_lanes } } } */
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } } } } */
+/* Fails for variable-length SVE because we fall back to Advanced SIMD
+ and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_perm3_int && {! vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_load_lanes } } } */
/* { dg-final { scan-tree-dump "note: Built SLP cancelled: can use load/store-lanes" "vect" { target { vect_perm3_int && vect_load_lanes } } } } */
/* { dg-final { scan-tree-dump "LOAD_LANES" "vect" { target vect_load_lanes } } } */
return 0;
}
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" { target { ! { vect_perm_short || vect_load_lanes } } } } } */
+/* Fails for variable-length SVE because we fall back to Advanced SIMD
+ and use LD3/ST3. Will be fixed when SVE LOAD_LANES support is added. */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" { target { ! { vect_perm_short || vect_load_lanes } } xfail { aarch64_sve && vect_variable_length } } } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_perm_short || vect_load_lanes } } } } */
/* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target { vect_perm_short && { ! vect_perm3_short } } } } } */
/* { dg-final { scan-tree-dump-not "permutation requires at least three vectors" "vect" { target vect_perm3_short } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { { ! vect_perm3_short } || vect_load_lanes } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_perm3_short && { ! vect_load_lanes } } } } } */
-
/* The initialization loop in main also gets vectorized. */
/* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_short_mult && { vect_widen_sum_hi_to_si && vect_unpack } } } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { ! vect_unpack } } } } } */
+/* We can't yet create the necessary SLP constant vector for variable-length
+ SVE and so fall back to Advanced SIMD. This means that we repeat each
+ analysis note. */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { xfail { vect_widen_sum_hi_to_si_pattern || { { ! vect_unpack } || { aarch64_sve && vect_variable_length } } } } } } */
signal (SIGILL, SIG_DFL);
}
-#define VECTOR_BITS 128
+#if defined (__ARM_FEATURE_SVE)
+# if __ARM_FEATURE_SVE_BITS == 0
+# define VECTOR_BITS 1024
+# else
+# define VECTOR_BITS __ARM_FEATURE_SVE_BITS
+# endif
+#else
+# define VECTOR_BITS 128
+#endif
return main1 ();
}
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_perm } } } } } */
+/* Requires reverse for SVE, which is implemented by a later patch.
+ Until then we fall back to Advanced SIMD and successfully vectorize
+ the loop. */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_perm } xfail { aarch64_sve && vect_variable_length } } } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_perm } } } */
return 0;
}
-/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* xfail aarch64_sve } } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target aarch64*-*-* } } } */
return 0;
}
-/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* } } } */
+/* { dg-final { scan-tree-dump-times "vect_recog_mult_pattern: detected" 2 "vect" { target aarch64*-*-* xfail aarch64_sve } } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target aarch64*-*-* } } } */
}]
}
+# Return 1 if this is an AArch64 target supporting SVE.
+proc check_effective_target_aarch64_sve { } {
+ if { ![istarget aarch64*-*-*] } {
+ return 0
+ }
+ return [check_no_compiler_messages aarch64_sve assembly {
+ #if !defined (__ARM_FEATURE_SVE)
+ #error FOO
+ #endif
+ }]
+}
+
+# Return the size in bits of an SVE vector, or 0 if the size is variable.
+proc aarch64_sve_bits { } {
+ return [check_cached_effective_target aarch64_sve_bits {
+ global tool
+
+ set src dummy[pid].c
+ set f [open $src "w"]
+ puts $f "int bits = __ARM_FEATURE_SVE_BITS;"
+ close $f
+ set output [${tool}_target_compile $src "" preprocess ""]
+ file delete $src
+
+ regsub {.*bits = ([^;]*);.*} $output {\1} bits
+ expr { $bits }
+ }]
+}
+
# Return 1 if this is a compiler supporting ARC atomic operations
proc check_effective_target_arc_atomic { } {
return [check_no_compiler_messages arc_atomic assembly {
} [add_options_for_arm_neon ""]]
}
+# Return true if this is an AArch64 target that can run SVE code.
+
+proc check_effective_target_aarch64_sve_hw { } {
+ if { ![istarget aarch64*-*-*] } {
+ return 0
+ }
+ return [check_runtime aarch64_sve_hw_available {
+ int
+ main (void)
+ {
+ asm volatile ("ptrue p0.b");
+ return 0;
+ }
+ }]
+}
+
+# Return true if this is an AArch64 target that can run SVE code and
+# if its SVE vectors have exactly BITS bits.
+
+proc aarch64_sve_hw_bits { bits } {
+ if { ![check_effective_target_aarch64_sve_hw] } {
+ return 0
+ }
+ return [check_runtime aarch64_sve${bits}_hw [subst {
+ int
+ main (void)
+ {
+ int res;
+ asm volatile ("cntd %0" : "=r" (res));
+ if (res * 64 != $bits)
+ __builtin_abort ();
+ return 0;
+ }
+ }]]
+}
+
+# Return true if this is an AArch64 target that can run SVE code and
+# if its SVE vectors have exactly 256 bits.
+
+proc check_effective_target_aarch64_sve256_hw { } {
+ return [aarch64_sve_hw_bits 256]
+}
+
proc check_effective_target_arm_neonv2_hw { } {
return [check_runtime arm_neon_hwv2_available {
#include "arm_neon.h"
} else {
set et_vect_perm_saved($et_index) 0
if { [is-effective-target arm_neon]
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![check_effective_target_vect_variable_length])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*]
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
if { ([is-effective-target arm_neon]
&& [is-effective-target arm_little_endian])
|| ([istarget aarch64*-*-*]
- && [is-effective-target aarch64_little_endian])
+ && [is-effective-target aarch64_little_endian]
+ && ![check_effective_target_vect_variable_length])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*]
|| ([istarget mips-*.*]
if { ([is-effective-target arm_neon]
&& [is-effective-target arm_little_endian])
|| ([istarget aarch64*-*-*]
- && [is-effective-target aarch64_little_endian])
+ && [is-effective-target aarch64_little_endian]
+ && ![check_effective_target_vect_variable_length])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*]
|| ([istarget mips*-*-*]
} else {
set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 0
if { [istarget powerpc*-*-*]
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![check_effective_target_aarch64_sve])
|| [is-effective-target arm_neon]
|| [istarget ia64-*-*] } {
set et_vect_widen_sum_hi_to_si_pattern_saved($et_index) 1
set et_vect_widen_mult_qi_to_hi_saved($et_index) 0
}
if { [istarget powerpc*-*-*]
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![check_effective_target_aarch64_sve])
|| [is-effective-target arm_neon]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) } {
if { [istarget powerpc*-*-*]
|| [istarget spu-*-*]
|| [istarget ia64-*-*]
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![check_effective_target_aarch64_sve])
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [is-effective-target arm_neon]
|| ([istarget s390*-*-*]
# alignment during vectorization.
proc check_effective_target_vect_element_align_preferred { } {
- return [check_effective_target_vect_variable_length]
+ return [expr { [check_effective_target_aarch64_sve]
+ && [check_effective_target_vect_variable_length] }]
}
# Return 1 if we can align stack data to the preferred vector alignment.
proc check_effective_target_vect_align_stack_vars { } {
+ if { [check_effective_target_aarch64_sve] } {
+ return [check_effective_target_vect_variable_length]
+ }
return 1
}
} else {
set et_vect_load_lanes 0
if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok])
- || [istarget aarch64*-*-*] } {
+ || ([istarget aarch64*-*-*]
+ && ![check_effective_target_aarch64_sve]) } {
set et_vect_load_lanes 1
}
}
# Return 1 if the target supports vector masked stores.
proc check_effective_target_vect_masked_store { } {
- return 0
+ return [check_effective_target_aarch64_sve]
}
# Return 1 if the target supports vector conditional operations, 0 otherwise.
proc available_vector_sizes { } {
set result {}
if { [istarget aarch64*-*-*] } {
+ if { [check_effective_target_aarch64_sve] } {
+ lappend result [aarch64_sve_bits]
+ }
lappend result 128 64
} elseif { [istarget arm*-*-*]
&& [check_effective_target_arm_neon_ok] } {
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