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diff --git a/docs/learning_nmigen.mdwn b/docs/learning_nmigen.mdwn
index 14e7bffa150d003fcb9489f24f6efd401c4e7775..8f21b9b8d58570739857e93febe3a38ec5c7d9bf 100644 (file)
--- a/docs/learning_nmigen.mdwn
+++ b/docs/learning_nmigen.mdwn
@@ -17,7 +17,9 @@
 * nMigen code for counter and testbench here: <https://nmigen.info/nmigen/latest/start.html>
 
 1. Create a file called "up_counter.py" containing the 16-bit up counter code from "Implementing a counter" section.
+
 1. Create a file called "tb_up_counter.py" containing the testbench from "Testing a counter".
+
 1. To the testbench file, add the import statement for the counter module (better get used to separating your sim/stimulus and module classes from the beginning):
 
     from up_counter import UpCounter
@@ -56,4 +58,4 @@
 
 1. Now you can improve your understanding with the nMigen, verilog, and block diagram views side-by-side!
 
-[[!img nmigen_verilog_tb.png ]]
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+[[!img nmigen_verilog_tb.png size="600x"]]
\ No newline at end of file