radeon/llvm: Sort tgsi opcode action initialization

This was done in order to identify and remove duplicate entries.

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index ee5bc00ab274de23e743a57e1f0f01e933901dc0..5e3d6c20be0cff9007cbf09d0fd57e30aa57e7f2 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1068,73 +1068,26 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 
        lp_set_default_actions(bld_base);
 
-       bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
-       bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
-       bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
-       bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
-       bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
-       bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
-       bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
-       bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
-       bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
-       bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
-       bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
-       bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
-       bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
-       bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
-       bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
-       bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
-       bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
-       bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
-       bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
-       bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
-       bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
-       bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
-       bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
-       bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
-       bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
-       bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
-       bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
-       bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
-       bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
-       bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
-       bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
-       bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
-       bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
-       bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
-       bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
-       bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
-       bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
-       bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
-       bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
-       bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
-       bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
-       bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
-       bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
-
-
-
        bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
        bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
        bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
+       bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
        bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
        bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
-       bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
+       bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
+       bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
        bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
        bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
+       bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
        bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly;
        bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
+       bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
+       bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
+       bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
+       bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
        bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
@@ -1146,7 +1099,22 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
        bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
+       bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
+       bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
+       bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
+       bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
        bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
+       bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
+       bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
+       bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
+       bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
+       bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
+       bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
+       bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
+       bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
        bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
        bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
        bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
@@ -1155,40 +1123,63 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
        bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
-       bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
        bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad.";
        bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
+       bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
+       bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
        bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
+       bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
+       bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
        bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
        bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
        bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
-       bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg";
+       bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
        bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
+       bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
        bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly;
        bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
+       bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
        bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
        bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
        bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
+       bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
+       bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
        bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
        bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
+       bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
+       bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
        bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
+       bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
+       bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
+       bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
+       bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
+       bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
+       bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
+       bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
+       bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
+       bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
+       bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
+       bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
+       bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
+       bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
 
        bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
        bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";