Fix default clock domain for gramNativePort

diff --git a/gram/common.py b/gram/common.py
index 1369c1915f6ef566886274149f07ad4beae11ec3..73012356f8437125fcb8d6942e81fb4c61fc3bb6 100644 (file)
--- a/gram/common.py
+++ b/gram/common.py
@@ -302,7 +302,7 @@ class gramInterface(Record):
 
 
 class gramNativePort(Settings):
-    def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0):
+    def __init__(self, mode, address_width, data_width, clock_domain="sync", id=0):
         self.set_attributes(locals())
 
         self.lock = Signal()