LIBDRM_INTEL_REQUIRED=2.4.75
LIBDRM_NVVIEUX_REQUIRED=2.4.66
LIBDRM_NOUVEAU_REQUIRED=2.4.66
-LIBDRM_FREEDRENO_REQUIRED=2.4.74
+LIBDRM_FREEDRENO_REQUIRED=2.4.89
LIBDRM_ETNAVIV_REQUIRED=2.4.82
dnl Versions for external dependencies
dep_libdrm_etnaviv = dependency('libdrm_etnaviv', version : '>= 2.4.82')
endif
if with_gallium_freedreno
- dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 2.4.74')
+ dep_libdrm_freedreno = dependency('libdrm_freedreno', version : '>= 2.4.89')
endif
llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
{
struct fd_screen *screen = fd_screen(pscreen);
struct pipe_context *pctx;
+ unsigned prio = 1;
int i;
+ /* lower numerical value == higher priority: */
+ if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
+ prio = 0;
+ else if (flags & PIPE_CONTEXT_LOW_PRIORITY)
+ prio = 2;
+
ctx->screen = screen;
- ctx->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
+ ctx->pipe = fd_pipe_new2(screen->dev, FD_PIPE_3D, prio);
ctx->primtypes = primtypes;
ctx->primtype_mask = 0;
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
- case PIPE_CAP_CONTEXT_PRIORITY_MASK:
return 0;
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ return screen->priority_mask;
+
case PIPE_CAP_DRAW_INDIRECT:
if (is_a4xx(screen) || is_a5xx(screen))
return 1;
}
screen->chip_id = val;
+ if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
+ DBG("could not get # of rings");
+ screen->priority_mask = 0;
+ } else {
+ /* # of rings equates to number of unique priority values: */
+ screen->priority_mask = (1 << val) - 1;
+ }
+
DBG("Pipe Info:");
DBG(" GPU-id: %d", screen->gpu_id);
DBG(" Chip-id: 0x%08x", screen->chip_id);
uint32_t max_rts; /* max # of render targets */
uint32_t gmem_alignw, gmem_alignh;
uint32_t num_vsc_pipes;
+ uint32_t priority_mask;
bool has_timestamp;
void *compiler; /* currently unused for a2xx */