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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 542fac162028bc7a3e239ee4e44db2f51b3cbd85..0b5397b08818f2d1c654c9a08f7bd92c25702d35 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -83,7 +83,7 @@ Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised
 | n/a     | Saturating Shift left logical       | VSLL (r2 <= rt,ra,rb <= r15), mm=01|
 | n/a     | Saturating Shift left logical imm   | VSLLI (r2 <= rt,ra <= r15), mm=01|
 
-## 16-bit Comparison
+## 16-bit Comparison instructions
 
 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
 | ------------------   | ------------------------- | ------------------- |
@@ -92,3 +92,13 @@ Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised
 | SCMPLE16 rt, ra, rb   | Signed Compare less or equal    | VSLE (r16 <= rt,ra,rb <= r23), mm=00|
 | UCMPLT16 rt, ra, rb   | Unsigned Compare less than      | !VSGT (r24 <= rt,ra,rb <= r29), mm=00|
 | UCMPLE16 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (r24 <= rt,ra,rb <= r29), mm=00|
+
+## 8-bit Comparison instructions
+
+| Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
+| ------------------   | ------------------------- | ------------------- |
+| CMPEQ8 rt, ra, rb   | Compare equal             | VSEQ (r2 <= rt,ra,rb <= r7), mm=00|
+| SCMPLT8 rt, ra, rb   | Signed Compare less than        | !VSGT (r2 <= rt,ra,rb <= r7), mm=00|
+| SCMPLE8 rt, ra, rb   | Signed Compare less or equal    | VSLE (r2 <= rt,ra,rb <= r7), mm=00|
+| UCMPLT8 rt, ra, rb   | Unsigned Compare less than      | !VSGT (r8 <= rt,ra,rb <= r15), mm=00|
+| UCMPLE8 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (r8 <= rt,ra,rb <= r15), mm=00|