bus/asmibus: fix per-port tag generation

diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py
index d98693b662ce3491a21570a36e68f5650c3d2c2c..39a60b35efb703974b54a056b8eba53762ebac20 100644 (file)
--- a/migen/bus/asmibus.py
+++ b/migen/bus/asmibus.py
@@ -101,9 +101,11 @@ class Port:
                                s.allocate_adr.eq(self.adr)
                        ]
                choose_slot = None
-               for s in reversed(self.slots):
+               needs_tags = len(self.slots) > 1
+               for n, s in reversed(list(enumerate(self.slots))):
                        choose_slot = If(s.state == SLOT_EMPTY,
-                               s.allocate.eq(self.stb)
+                               s.allocate.eq(self.stb),
+                               self.tag_issue.eq(n) if needs_tags else None
                        ).Else(choose_slot)
                comb.append(choose_slot)
                comb.append(self.ack.eq(optree("|",