+++ /dev/null
-logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
-read_verilog << EOF
-module top(...);
- assign b = w;
-endmodule
-EOF
+++ /dev/null
-logger -expect-no-warnings -nowarn "is implicitly declared."
-read_verilog << EOF
-module top(...);
- assign b = w;
-endmodule
-EOF
+++ /dev/null
-logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
-read_verilog << EOF
-module top(...);
- assign b = w;
-endmodule
-EOF
+++ /dev/null
-logger -expect warning "is implicitly declared." 2
-read_verilog << EOF
-module top(...);
- assign b = w;
-endmodule
-EOF