case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
+ case AARCH64_OPND_SME_Zm_INDEX1:
+ case AARCH64_OPND_SME_Zm_INDEX2:
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
case AARCH64_OPND_SME_Zn_INDEX2_16:
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-11-invalid.s
+#error_output: sme2-11-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmla 0,{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fmla za\.s\[w8,0\],0,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},0'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s'
+[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.s\[w8,0\],{z0-z1},z0\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
--- /dev/null
+ fmla 0, { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 0], 0, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z1.s }, 0
+
+ fmla za.s[w7, 0], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w12, 0], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, -1], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 8], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z2.s }, z0.s[0]
+ fmla za.s[w8, 0], { z1.s - z2.s }, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z1.s }, z16.s[0]
+ fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[-1]
+ fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[4]
+
+ fmla za.s[w7, 0], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w12, 0], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, -1], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, 8], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z4.s }, z0.s[0]
+ fmla za.s[w8, 0], { z1.s - z4.s }, z0.s[0]
+ fmla za.s[w8, 0], { z2.s - z5.s }, z0.s[0]
+ fmla za.s[w8, 0], { z3.s - z6.s }, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z3.s }, z16.s[0]
+ fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[-1]
+ fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[4]
+
+ fmla za.s[w0, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w31, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 1<<63], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0], { z0.s - z1.s }, z31.s
+ fmla za.s[w8, 0:0], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0:-1], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0:1], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0:100], { z0.s - z1.s }, z0.s
+
+ fmla za.s[w7, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w12, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, -1], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 8], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0], { z0.s - z1.s }, z16.s
+
+ fmla za.s[w7, 0], { z0.s - z3.s }, z0.s
+ fmla za.s[w12, 0], { z0.s - z3.s }, z0.s
+ fmla za.s[w8, -1], { z0.s - z3.s }, z0.s
+ fmla za.s[w8, 8], { z0.s - z3.s }, z0.s
+ fmla za.s[w8, 0], { z0.s - z3.s }, z16.s
+
+ fmla za.s[w8, 0], { z0.s - z2.s }, z0.s
+ fmla za.s[w8, 0], { z0.s - z4.s }, z0.s
+ fmla za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s
+ fmla za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s
+
+ fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s
+ fmla za[w8, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0], { z0 - z1 }, z0.s
+ fmla za.s[w8, 0], { z0.s - z1.s }, z0
+ fmla za[w8, 0], { z0.s - z1.s }, z0
+
+ fmla za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s }
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s }
+
+ fmla za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s }
+ fmla za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s }
+
+ fmla za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s }
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s }
+
+ fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s }
+ fmla za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-11.s
+#error_output: sme2-11-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1506000 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1500007 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c15003c0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\]
+[^:]+: c15f0000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\]
+[^:]+: c1500c00 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\]
+[^:]+: c1512986 fmla za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\]
+[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c150e000 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508007 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508380 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\]
+[^:]+: c15f8000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\]
+[^:]+: c1508c00 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\]
+[^:]+: c159c484 fmla za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\]
+[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1207800 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201807 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201bc0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
+[^:]+: c1201be0 fmla za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+: c1201be0 fmla za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+: c12f1800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
+[^:]+: c1263925 fmla za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
+[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1307800 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301807 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301b80 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
+[^:]+: c1301be0 fmla za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+: c1301be0 fmla za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+: c13f1800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
+[^:]+: c13d7ae2 fmla za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
+[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a07800 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01807 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01bc0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+: c1be1800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+: c1b25ac1 fmla za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
+[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a17800 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11807 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11b80 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+: c1bd1800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+: c1b97a03 fmla za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
+[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1506010 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c1500017 fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+: c15003d0 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\]
+[^:]+: c15f0010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\]
+[^:]+: c1500c10 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\]
+[^:]+: c1512996 fmls za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\]
+[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c150e010 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508017 fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+: c1508390 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\]
+[^:]+: c15f8010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\]
+[^:]+: c1508c10 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\]
+[^:]+: c159c494 fmls za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\]
+[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1207808 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c120180f fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+: c1201bc8 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
+[^:]+: c1201be8 fmls za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+: c1201be8 fmls za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+: c12f1808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
+[^:]+: c126392d fmls za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
+[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1307808 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c130180f fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+: c1301b88 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
+[^:]+: c1301be8 fmls za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+: c1301be8 fmls za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+: c13f1808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
+[^:]+: c13d7aea fmls za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
+[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a07808 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a0180f fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a01bc8 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+: c1be1808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+: c1b25ac9 fmls za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
+[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a17808 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a1180f fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a11b88 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+: c1bd1808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+: c1b97a0b fmls za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
--- /dev/null
+ fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0]
+ FMLA ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0]
+ fmla za.s[w11, 0], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 7], { z0.s - z1.s }, z0.s[0]
+ fmla za.s[w8, 0], { z30.s - z31.s }, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z1.s }, z15.s[0]
+ fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[3]
+ fmla za.s[w9, 6], { z12.s - z13.s }, z1.s[2]
+
+ fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+ FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]
+ fmla za.s[w11, 0], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, 7], { z0.s - z3.s }, z0.s[0]
+ fmla za.s[w8, 0], { z28.s - z31.s }, z0.s[0]
+ fmla za.s[w8, 0], { z0.s - z3.s }, z15.s[0]
+ fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[3]
+ fmla za.s[w10, 4], { z4.s - z7.s }, z9.s[1]
+
+ fmla za.s[w8, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
+ FMLA ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
+ FMLA ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
+ fmla za.s[w11, 0], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 7], { z0.s - z1.s }, z0.s
+ fmla za.s[w8, 0], { z30.s - z31.s }, z0.s
+ fmla za.s[w8, 0], { z31.s, z0.s }, z0.s
+ fmla za.s[w8, 0], { z31.s - z0.s }, z0.s
+ fmla za.s[w8, 0], { z0.s - z1.s }, z15.s
+ fmla za.s[w9, 5], { z9.s - z10.s }, z6.s
+
+ fmla za.s[w8, 0], { z0.s - z3.s }, z0.s
+ fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
+ FMLA ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
+ FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
+ fmla za.s[w11, 0], { z0.s - z3.s }, z0.s
+ fmla za.s[w8, 7], { z0.s - z3.s }, z0.s
+ fmla za.s[w8, 0], { z28.s - z31.s }, z0.s
+ fmla za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
+ fmla za.s[w8, 0], { z31.s - z2.s }, z0.s
+ fmla za.s[w8, 0], { z0.s - z3.s }, z15.s
+ fmla za.s[w11, 2], { z23.s - z26.s }, z13.s
+
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
+ FMLA ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
+ FMLA ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
+ fmla za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
+ fmla za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
+ fmla za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
+
+ fmla za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+ FMLA ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
+ FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
+ fmla za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
+ fmla za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
+ fmla za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
+
+ fmls za.s[w8, 0], { z0.s - z1.s }, z0.s[0]
+ fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0]
+ FMLS ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0]
+ fmls za.s[w11, 0], { z0.s - z1.s }, z0.s[0]
+ fmls za.s[w8, 7], { z0.s - z1.s }, z0.s[0]
+ fmls za.s[w8, 0], { z30.s - z31.s }, z0.s[0]
+ fmls za.s[w8, 0], { z0.s - z1.s }, z15.s[0]
+ fmls za.s[w8, 0], { z0.s - z1.s }, z0.s[3]
+ fmls za.s[w9, 6], { z12.s - z13.s }, z1.s[2]
+
+ fmls za.s[w8, 0], { z0.s - z3.s }, z0.s[0]
+ fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+ FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]
+ fmls za.s[w11, 0], { z0.s - z3.s }, z0.s[0]
+ fmls za.s[w8, 7], { z0.s - z3.s }, z0.s[0]
+ fmls za.s[w8, 0], { z28.s - z31.s }, z0.s[0]
+ fmls za.s[w8, 0], { z0.s - z3.s }, z15.s[0]
+ fmls za.s[w8, 0], { z0.s - z3.s }, z0.s[3]
+ fmls za.s[w10, 4], { z4.s - z7.s }, z9.s[1]
+
+ fmls za.s[w8, 0], { z0.s - z1.s }, z0.s
+ fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
+ FMLS ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
+ FMLS ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
+ fmls za.s[w11, 0], { z0.s - z1.s }, z0.s
+ fmls za.s[w8, 7], { z0.s - z1.s }, z0.s
+ fmls za.s[w8, 0], { z30.s - z31.s }, z0.s
+ fmls za.s[w8, 0], { z31.s, z0.s }, z0.s
+ fmls za.s[w8, 0], { z31.s - z0.s }, z0.s
+ fmls za.s[w8, 0], { z0.s - z1.s }, z15.s
+ fmls za.s[w9, 5], { z9.s - z10.s }, z6.s
+
+ fmls za.s[w8, 0], { z0.s - z3.s }, z0.s
+ fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
+ FMLS ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
+ FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
+ fmls za.s[w11, 0], { z0.s - z3.s }, z0.s
+ fmls za.s[w8, 7], { z0.s - z3.s }, z0.s
+ fmls za.s[w8, 0], { z28.s - z31.s }, z0.s
+ fmls za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
+ fmls za.s[w8, 0], { z31.s - z2.s }, z0.s
+ fmls za.s[w8, 0], { z0.s - z3.s }, z15.s
+ fmls za.s[w11, 2], { z23.s - z26.s }, z13.s
+
+ fmls za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
+ FMLS ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
+ FMLS ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
+ fmls za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
+ fmls za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
+ fmls za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
+ fmls za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
+ fmls za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
+
+ fmls za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
+ fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+ FMLS ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
+ FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
+ fmls za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
+ fmls za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
+ fmls za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
+ fmls za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
+ fmls za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-f64f64-2-invalid.s
+#error_output: sme2-f64f64-2-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d'
+[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.d\[w8,0:0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.d\[w8,0:-1\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:1\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:100\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.d\[w8,0\],{z0-z1},z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
--- /dev/null
+ fmla za.d[w7, 0], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w12, 0], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, -1], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, 8], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, 0], { z0.d - z2.d }, z0.d[0]
+ fmla za.d[w8, 0], { z1.d - z2.d }, z0.d[0]
+ fmla za.d[w8, 0], { z0.d - z1.d }, z16.d[0]
+ fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[-1]
+ fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[2]
+
+ fmla za.d[w7, 0], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w12, 0], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, -1], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, 8], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, 0], { z0.d - z4.d }, z0.d[0]
+ fmla za.d[w8, 0], { z1.d - z4.d }, z0.d[0]
+ fmla za.d[w8, 0], { z2.d - z5.d }, z0.d[0]
+ fmla za.d[w8, 0], { z3.d - z6.d }, z0.d[0]
+ fmla za.d[w8, 0], { z0.d - z3.d }, z16.d[0]
+ fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[-1]
+ fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[2]
+
+ fmla za.d[w0, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w31, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 1<<63], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0], { z0.d - z1.d }, z31.d
+ fmla za.d[w8, 0:0], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0:-1], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0:1], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0:100], { z0.d - z1.d }, z0.d
+
+ fmla za.d[w7, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w12, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, -1], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 8], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0], { z0.d - z1.d }, z16.d
+
+ fmla za.d[w7, 0], { z0.d - z3.d }, z0.d
+ fmla za.d[w12, 0], { z0.d - z3.d }, z0.d
+ fmla za.d[w8, -1], { z0.d - z3.d }, z0.d
+ fmla za.d[w8, 8], { z0.d - z3.d }, z0.d
+ fmla za.d[w8, 0], { z0.d - z3.d }, z16.d
+
+ fmla za.d[w8, 0], { z0.d - z2.d }, z0.d
+ fmla za.d[w8, 0], { z0.d - z4.d }, z0.d
+ fmla za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d
+ fmla za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d
+
+ fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d
+ fmla za[w8, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0], { z0 - z1 }, z0.d
+ fmla za.d[w8, 0], { z0.d - z1.d }, z0
+ fmla za[w8, 0], { z0.d - z1.d }, z0
+
+ fmla za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0], { z1.d - z2.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d }
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d }
+
+ fmla za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d }
+ fmla za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d }
+
+ fmla za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d }
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d }
+
+ fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d }
+ fmla za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
--- /dev/null
+#as: -march=armv8-a+sme2
+#source: sme2-f64f64-2.s
+#error_output: sme2-f64f64-2-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
--- /dev/null
+#as: -march=armv8-a+sme2+sme-f64f64
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d06000 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d00007 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d003c0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\]
+[^:]+: c1df0000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\]
+[^:]+: c1d00400 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\]
+[^:]+: c1d544c2 fmla za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\]
+[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d0e000 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08007 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08380 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\]
+[^:]+: c1df8000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\]
+[^:]+: c1d08400 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\]
+[^:]+: c1dea503 fmla za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\]
+[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1607800 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601807 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601bc0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
+[^:]+: c1601be0 fmla za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+: c1601be0 fmla za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+: c16f1800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
+[^:]+: c1663925 fmla za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
+[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1707800 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701807 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701b80 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
+[^:]+: c1701be0 fmla za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+: c1701be0 fmla za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+: c17f1800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
+[^:]+: c17d7ae2 fmla za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
+[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e07800 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01807 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01bc0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
+[^:]+: c1fe1800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
+[^:]+: c1f25ac1 fmla za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
+[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e17800 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11807 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11b80 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
+[^:]+: c1fd1800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
+[^:]+: c1f97a03 fmla za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
+[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d06010 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d00017 fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+: c1d003d0 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\]
+[^:]+: c1df0010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\]
+[^:]+: c1d00410 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\]
+[^:]+: c1d544d2 fmls za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\]
+[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d0e010 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08017 fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+: c1d08390 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\]
+[^:]+: c1df8010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\]
+[^:]+: c1d08410 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\]
+[^:]+: c1dea513 fmls za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\]
+[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1607808 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c160180f fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+: c1601bc8 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
+[^:]+: c1601be8 fmls za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+: c1601be8 fmls za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+: c16f1808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
+[^:]+: c166392d fmls za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
+[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1707808 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c170180f fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+: c1701b88 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
+[^:]+: c1701be8 fmls za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+: c1701be8 fmls za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+: c17f1808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
+[^:]+: c17d7aea fmls za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
+[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e07808 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e0180f fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e01bc8 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
+[^:]+: c1fe1808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
+[^:]+: c1f25ac9 fmls za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
+[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e17808 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e1180f fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e11b88 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
+[^:]+: c1fd1808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
+[^:]+: c1f97a0b fmls za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
--- /dev/null
+ fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]
+ FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]
+ fmla za.d[w11, 0], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, 7], { z0.d - z1.d }, z0.d[0]
+ fmla za.d[w8, 0], { z30.d - z31.d }, z0.d[0]
+ fmla za.d[w8, 0], { z0.d - z1.d }, z15.d[0]
+ fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[1]
+ fmla za.d[w10, 2], { z6.d - z7.d }, z5.d[1]
+
+ fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+ FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]
+ fmla za.d[w11, 0], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, 7], { z0.d - z3.d }, z0.d[0]
+ fmla za.d[w8, 0], { z28.d - z31.d }, z0.d[0]
+ fmla za.d[w8, 0], { z0.d - z3.d }, z15.d[0]
+ fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[1]
+ fmla za.d[w9, 3], { z8.d - z11.d }, z14.d[1]
+
+ fmla za.d[w8, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
+ FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
+ FMLA ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
+ fmla za.d[w11, 0], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 7], { z0.d - z1.d }, z0.d
+ fmla za.d[w8, 0], { z30.d - z31.d }, z0.d
+ fmla za.d[w8, 0], { z31.d, z0.d }, z0.d
+ fmla za.d[w8, 0], { z31.d - z0.d }, z0.d
+ fmla za.d[w8, 0], { z0.d - z1.d }, z15.d
+ fmla za.d[w9, 5], { z9.d - z10.d }, z6.d
+
+ fmla za.d[w8, 0], { z0.d - z3.d }, z0.d
+ fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
+ FMLA ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
+ FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
+ fmla za.d[w11, 0], { z0.d - z3.d }, z0.d
+ fmla za.d[w8, 7], { z0.d - z3.d }, z0.d
+ fmla za.d[w8, 0], { z28.d - z31.d }, z0.d
+ fmla za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
+ fmla za.d[w8, 0], { z31.d - z2.d }, z0.d
+ fmla za.d[w8, 0], { z0.d - z3.d }, z15.d
+ fmla za.d[w11, 2], { z23.d - z26.d }, z13.d
+
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
+ FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
+ FMLA ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
+ fmla za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
+ fmla za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
+ fmla za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
+
+ fmla za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+ FMLA ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
+ FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
+ fmla za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
+ fmla za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
+ fmla za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }
+
+ fmls za.d[w8, 0], { z0.d - z1.d }, z0.d[0]
+ fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]
+ FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]
+ fmls za.d[w11, 0], { z0.d - z1.d }, z0.d[0]
+ fmls za.d[w8, 7], { z0.d - z1.d }, z0.d[0]
+ fmls za.d[w8, 0], { z30.d - z31.d }, z0.d[0]
+ fmls za.d[w8, 0], { z0.d - z1.d }, z15.d[0]
+ fmls za.d[w8, 0], { z0.d - z1.d }, z0.d[1]
+ fmls za.d[w10, 2], { z6.d - z7.d }, z5.d[1]
+
+ fmls za.d[w8, 0], { z0.d - z3.d }, z0.d[0]
+ fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+ FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]
+ fmls za.d[w11, 0], { z0.d - z3.d }, z0.d[0]
+ fmls za.d[w8, 7], { z0.d - z3.d }, z0.d[0]
+ fmls za.d[w8, 0], { z28.d - z31.d }, z0.d[0]
+ fmls za.d[w8, 0], { z0.d - z3.d }, z15.d[0]
+ fmls za.d[w8, 0], { z0.d - z3.d }, z0.d[1]
+ fmls za.d[w9, 3], { z8.d - z11.d }, z14.d[1]
+
+ fmls za.d[w8, 0], { z0.d - z1.d }, z0.d
+ fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
+ FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
+ FMLS ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
+ fmls za.d[w11, 0], { z0.d - z1.d }, z0.d
+ fmls za.d[w8, 7], { z0.d - z1.d }, z0.d
+ fmls za.d[w8, 0], { z30.d - z31.d }, z0.d
+ fmls za.d[w8, 0], { z31.d, z0.d }, z0.d
+ fmls za.d[w8, 0], { z31.d - z0.d }, z0.d
+ fmls za.d[w8, 0], { z0.d - z1.d }, z15.d
+ fmls za.d[w9, 5], { z9.d - z10.d }, z6.d
+
+ fmls za.d[w8, 0], { z0.d - z3.d }, z0.d
+ fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
+ FMLS ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
+ FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
+ fmls za.d[w11, 0], { z0.d - z3.d }, z0.d
+ fmls za.d[w8, 7], { z0.d - z3.d }, z0.d
+ fmls za.d[w8, 0], { z28.d - z31.d }, z0.d
+ fmls za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
+ fmls za.d[w8, 0], { z31.d - z2.d }, z0.d
+ fmls za.d[w8, 0], { z0.d - z3.d }, z15.d
+ fmls za.d[w11, 2], { z23.d - z26.d }, z13.d
+
+ fmls za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
+ FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
+ FMLS ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
+ fmls za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
+ fmls za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
+ fmls za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
+ fmls za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
+ fmls za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
+
+ fmls za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
+ fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+ FMLS ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
+ FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
+ fmls za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
+ fmls za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
+ fmls za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
+ fmls za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
+ fmls za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
+ AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
+ AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
case 33:
case 34:
case 35:
- case 257:
+ case 259:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 193:
case 194:
case 237:
- case 251:
- case 252:
+ case 253:
case 254:
case 256:
- case 261:
- case 262:
+ case 258:
+ case 263:
+ case 264:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
case 107:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 108:
- case 253:
case 255:
+ case 257:
return aarch64_ins_none (self, info, code, inst, errors);
case 109:
return aarch64_ins_hint (self, info, code, inst, errors);
case 248:
case 249:
case 250:
+ case 251:
+ case 252:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 239:
case 240:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 244:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
- case 258:
- case 259:
case 260:
+ case 261:
+ case 262:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
10987654321098765432109876543210
x1000000x10x100xxxxxxxxxxxxxxxxx
zero. */
- return 2658;
+ return 2670;
}
}
}
10987654321098765432109876543210
x1000000x00x101xx0xxxxxxxxxxxxxx
luti4. */
- return 2527;
+ return 2539;
}
else
{
10987654321098765432109876543210
x1000000x00x101xx1xxxxxxxxxxxxxx
luti4. */
- return 2526;
+ return 2538;
}
}
else
10987654321098765432109876543210
x1000000x10x101xxxxxxxxxxxxxxxxx
luti4. */
- return 2525;
+ return 2537;
}
}
}
10987654321098765432109876543210
x1000000xx0x010xxxxx00xxxxxxxxxx
mov. */
- return 2534;
+ return 2546;
}
else
{
10987654321098765432109876543210
x1000000xx0x011xxxxx00xxxxxxxxxx
mov. */
- return 2530;
+ return 2542;
}
}
else
10987654321098765432109876543210
x1000000x00x11xxx0xx00xxxxxxxxxx
luti2. */
- return 2524;
+ return 2536;
}
else
{
10987654321098765432109876543210
x1000000x00x11xxx1xx00xxxxxxxxxx
luti2. */
- return 2523;
+ return 2535;
}
}
else
10987654321098765432109876543210
x1000000010x110xxxxx00xxxxxxxxxx
movt. */
- return 2545;
+ return 2557;
}
else
{
10987654321098765432109876543210
x1000000010x111xxxxx00xxxxxxxxxx
movt. */
- return 2544;
+ return 2556;
}
}
else
10987654321098765432109876543210
x1000000110x11xxxxxx00xxxxxxxxxx
luti2. */
- return 2522;
+ return 2534;
}
}
}
10987654321098765432109876543210
x1000000xx0xx10xxxxx10xxxxxxxxxx
mov. */
- return 2532;
+ return 2544;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx10xxxxxxxxxx
mov. */
- return 2528;
+ return 2540;
}
}
}
10987654321098765432109876543210
x1000000xx0xx10xxxxx01xxxxxxxxxx
mov. */
- return 2535;
+ return 2547;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx01xxxxxxxxxx
mov. */
- return 2531;
+ return 2543;
}
}
else
10987654321098765432109876543210
x1000000xx0xx10xxxxx11xxxxxxxxxx
mov. */
- return 2533;
+ return 2545;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx11xxxxxxxxxx
mov. */
- return 2529;
+ return 2541;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2461;
+ return 2473;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2462;
+ return 2474;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2485;
+ return 2497;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2486;
+ return 2498;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2477;
+ return 2489;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2478;
+ return 2490;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2469;
+ return 2481;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2470;
+ return 2482;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2493;
+ return 2505;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2494;
+ return 2506;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2517;
+ return 2529;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2518;
+ return 2530;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2509;
+ return 2521;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2510;
+ return 2522;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2501;
+ return 2513;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2502;
+ return 2514;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2457;
+ return 2469;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2458;
+ return 2470;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2481;
+ return 2493;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2482;
+ return 2494;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2473;
+ return 2485;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2474;
+ return 2486;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2465;
+ return 2477;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2466;
+ return 2478;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2489;
+ return 2501;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2490;
+ return 2502;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2513;
+ return 2525;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2514;
+ return 2526;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2505;
+ return 2517;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2506;
+ return 2518;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2497;
+ return 2509;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2498;
+ return 2510;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2571;
+ return 2583;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2572;
+ return 2584;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2595;
+ return 2607;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2596;
+ return 2608;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2587;
+ return 2599;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2588;
+ return 2600;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2579;
+ return 2591;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2580;
+ return 2592;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2603;
+ return 2615;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2604;
+ return 2616;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2627;
+ return 2639;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2628;
+ return 2640;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2619;
+ return 2631;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2620;
+ return 2632;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2611;
+ return 2623;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2612;
+ return 2624;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2567;
+ return 2579;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2568;
+ return 2580;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2591;
+ return 2603;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2592;
+ return 2604;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2583;
+ return 2595;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2584;
+ return 2596;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2575;
+ return 2587;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2576;
+ return 2588;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2599;
+ return 2611;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2600;
+ return 2612;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2623;
+ return 2635;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2624;
+ return 2636;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2615;
+ return 2627;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2616;
+ return 2628;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2607;
+ return 2619;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2608;
+ return 2620;
}
}
}
10987654321098765432109876543210
x0x00001000xxxxx000xxxxxxxxx0xxx
ld1b. */
- return 2463;
+ return 2475;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx010xxxxxxxxx0xxx
ld1w. */
- return 2487;
+ return 2499;
}
}
else
10987654321098765432109876543210
x0x00001000xxxxx001xxxxxxxxx0xxx
ld1h. */
- return 2479;
+ return 2491;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx011xxxxxxxxx0xxx
ld1d. */
- return 2471;
+ return 2483;
}
}
}
10987654321098765432109876543210
x0x00001000xxxxx000xxxxxxxxx1xxx
ldnt1b. */
- return 2495;
+ return 2507;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx010xxxxxxxxx1xxx
ldnt1w. */
- return 2519;
+ return 2531;
}
}
else
10987654321098765432109876543210
x0x00001000xxxxx001xxxxxxxxx1xxx
ldnt1h. */
- return 2511;
+ return 2523;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx011xxxxxxxxx1xxx
ldnt1d. */
- return 2503;
+ return 2515;
}
}
}
10987654321098765432109876543210
x0x00001000xxxxx100xxxxxxxxx0xxx
ld1b. */
- return 2464;
+ return 2476;
}
else
{
10987654321098765432109876543210
x1x00001000xxxxx100xxxxxxxxx0xxx
ldr. */
- return 2521;
+ return 2533;
}
}
else
10987654321098765432109876543210
xxx00001000xxxxx110xxxxxxxxx0xxx
ld1w. */
- return 2488;
+ return 2500;
}
}
else
10987654321098765432109876543210
xxx00001000xxxxx101xxxxxxxxx0xxx
ld1h. */
- return 2480;
+ return 2492;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx111xxxxxxxxx0xxx
ld1d. */
- return 2472;
+ return 2484;
}
}
}
10987654321098765432109876543210
xxx00001000xxxxx100xxxxxxxxx1xxx
ldnt1b. */
- return 2496;
+ return 2508;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx110xxxxxxxxx1xxx
ldnt1w. */
- return 2520;
+ return 2532;
}
}
else
10987654321098765432109876543210
xxx00001000xxxxx101xxxxxxxxx1xxx
ldnt1h. */
- return 2512;
+ return 2524;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx111xxxxxxxxx1xxx
ldnt1d. */
- return 2504;
+ return 2516;
}
}
}
{
if (((word >> 3) & 0x1) == 0)
{
- if (((word >> 13) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001010xxxxx000xxxxxxxxx0xxx
- ld1b. */
- return 2459;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx000xxxxxxxxx0xxx
+ ld1b. */
+ return 2471;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx010xxxxxxxxx0xxx
+ ld1w. */
+ return 2495;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001010xxxxx100xxxxxxxxx0xxx
- ld1b. */
- return 2460;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx001xxxxxxxxx0xxx
+ ld1h. */
+ return 2487;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx011xxxxxxxxx0xxx
+ ld1d. */
+ return 2479;
+ }
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx00001010xxxxx010xxxxxxxxx0xxx
- ld1w. */
- return 2483;
+ xxx000010101xxxx0xxxxxxxxxx00xxx
+ fmla. */
+ return 2455;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx00001010xxxxx110xxxxxxxxx0xxx
- ld1w. */
- return 2484;
+ xxx000010101xxxx0xxxxxxxxxx10xxx
+ fmls. */
+ return 2461;
}
}
}
else
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001010xxxxx001xxxxxxxxx0xxx
- ld1h. */
- return 2475;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx100xxxxxxxxx0xxx
+ ld1b. */
+ return 2472;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx110xxxxxxxxx0xxx
+ ld1w. */
+ return 2496;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001010xxxxx101xxxxxxxxx0xxx
- ld1h. */
- return 2476;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx101xxxxxxxxx0xxx
+ ld1h. */
+ return 2488;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010100xxxx111xxxxxxxxx0xxx
+ ld1d. */
+ return 2480;
+ }
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx00001010xxxxx011xxxxxxxxx0xxx
- ld1d. */
- return 2467;
+ xxx000010101xxxx1xxxxxxxxxx00xxx
+ fmla. */
+ return 2456;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx00001010xxxxx111xxxxxxxxx0xxx
- ld1d. */
- return 2468;
+ xxx000010101xxxx1xxxxxxxxxx10xxx
+ fmls. */
+ return 2462;
}
}
}
10987654321098765432109876543210
xxx00001010xxxxx000xxxxxxxxx1xxx
ldnt1b. */
- return 2491;
+ return 2503;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx100xxxxxxxxx1xxx
ldnt1b. */
- return 2492;
+ return 2504;
}
}
else
10987654321098765432109876543210
xxx00001010xxxxx010xxxxxxxxx1xxx
ldnt1w. */
- return 2515;
+ return 2527;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx110xxxxxxxxx1xxx
ldnt1w. */
- return 2516;
+ return 2528;
}
}
}
10987654321098765432109876543210
xxx00001010xxxxx001xxxxxxxxx1xxx
ldnt1h. */
- return 2507;
+ return 2519;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx101xxxxxxxxx1xxx
ldnt1h. */
- return 2508;
+ return 2520;
}
}
else
10987654321098765432109876543210
xxx00001010xxxxx011xxxxxxxxx1xxx
ldnt1d. */
- return 2499;
+ return 2511;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx111xxxxxxxxx1xxx
ldnt1d. */
- return 2500;
+ return 2512;
}
}
}
{
if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00001110xxxxxxxxxxxxxxxx0xxxx
- usmopa. */
- return 2385;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx0xxxxxxxxxx0xxxx
+ fmla. */
+ return 2671;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx1xxxxxxxxxx0xxxx
+ fmla. */
+ return 2672;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00001110xxxxxxxxxxxxxxxx0xxxx
- ld1q. */
- return 2397;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001110xxxxxxxxxxxxxxxx0xxxx
+ usmopa. */
+ return 2385;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100001110xxxxxxxxxxxxxxxx0xxxx
+ ld1q. */
+ return 2397;
+ }
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001110xxxxxxxxxxxxxxxx1xxxx
- usmops. */
- return 2387;
+ if (((word >> 29) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx0xxxxxxxxxx1xxxx
+ fmls. */
+ return 2673;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx1xxxxxxxxxx1xxxx
+ fmls. */
+ return 2674;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001110xxxxxxxxxxxxxxxx1xxxx
+ usmops. */
+ return 2387;
+ }
}
}
}
{
if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx00xxxxxxxxxx00xxx
- fadd. */
- return 2437;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xxxx0xxxxx00xxx
+ fmla. */
+ return 2457;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xxxx0xxxxx00xxx
+ fmla. */
+ return 2458;
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xxxx0xxxxx00xxx
+ fmla. */
+ return 2459;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xxxx0xxxxx00xxx
+ fmla. */
+ return 2460;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx10xxxxxxxxxx00xxx
- fadd. */
- return 2438;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxx00xxxx1xxxxx00xxx
+ fadd. */
+ return 2437;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxx10xxxx1xxxxx00xxx
+ fadd. */
+ return 2438;
+ }
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000010x11xxxx0xxxx0xxxxx10xxx
- add. */
- return 2431;
+ x10000010x11xxxx0xxxx0xxxxx10xxx
+ add. */
+ return 2431;
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xxxx0xxxxx10xxx
+ add. */
+ return 2432;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xxxx0xxxxx10xxx
+ add. */
+ return 2433;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxx00xxxx1xxxxx10xxx
+ add. */
+ return 2428;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxx10xxxx1xxxxx10xxx
+ add. */
+ return 2429;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xxxx0xxxxx01xxx
+ fmls. */
+ return 2463;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xxxx0xxxxx01xxx
+ fmls. */
+ return 2464;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx00xxxx0xxxxx10xxx
- add. */
- return 2432;
+ x10000011x1xxxx00xxxx0xxxxx01xxx
+ fmls. */
+ return 2465;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx10xxxx0xxxxx10xxx
- add. */
- return 2433;
+ x10000011x1xxxx10xxxx0xxxxx01xxx
+ fmls. */
+ return 2466;
}
}
}
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxx00xxxx1xxxxx10xxx
- add. */
- return 2428;
+ x1000001xx1xxxx00xxxx1xxxxx01xxx
+ fsub. */
+ return 2467;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxx10xxxx1xxxxx10xxx
- add. */
- return 2429;
+ x1000001xx1xxxx10xxxx1xxxxx01xxx
+ fsub. */
+ return 2468;
}
}
}
- }
- else
- {
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 16) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx00xxxxxxxxxx01xxx
- fsub. */
- return 2455;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx10xxxxxxxxxx01xxx
- fsub. */
- return 2456;
- }
- }
else
{
if (((word >> 10) & 0x1) == 0)
10987654321098765432109876543210
x10000010x10xxxx0xxxx0xxxxx11xxx
sub. */
- return 2634;
+ return 2646;
}
else
{
10987654321098765432109876543210
x10000010x11xxxx0xxxx0xxxxx11xxx
sub. */
- return 2635;
+ return 2647;
}
}
else
10987654321098765432109876543210
x10000011x1xxxx00xxxx0xxxxx11xxx
sub. */
- return 2636;
+ return 2648;
}
else
{
10987654321098765432109876543210
x10000011x1xxxx10xxxx0xxxxx11xxx
sub. */
- return 2637;
+ return 2649;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxx00xxxx1xxxxx11xxx
sub. */
- return 2632;
+ return 2644;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxx10xxxx1xxxxx11xxx
sub. */
- return 2633;
+ return 2645;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxx01x0xxxxxxx0xxxx0
sel. */
- return 2549;
+ return 2561;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxx11x0xxxxxxx0xxxx0
sel. */
- return 2550;
+ return 2562;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1x1000x0xx0xxxx0
smax. */
- return 2551;
+ return 2563;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1x1100x0xx0xxxx0
smax. */
- return 2553;
+ return 2565;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1x1010x0xx0xxxx0
smax. */
- return 2552;
+ return 2564;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1x1110x0xx0xxxx0
smax. */
- return 2554;
+ return 2566;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1x1001x0xx0xxxx0
sqdmulh. */
- return 2559;
+ return 2571;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1x1101x0xx0xxxx0
sqdmulh. */
- return 2561;
+ return 2573;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1x1011x0xx0xxxx0
sqdmulh. */
- return 2560;
+ return 2572;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1x1111x0xx0xxxx0
sqdmulh. */
- return 2562;
+ return 2574;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1xx00x00xx1xxxx0
smin. */
- return 2555;
+ return 2567;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx10x00xx1xxxx0
smin. */
- return 2557;
+ return 2569;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1xx01x00xx1xxxx0
smin. */
- return 2556;
+ return 2568;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx11x00xx1xxxx0
smin. */
- return 2558;
+ return 2570;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1xx00x10xx1xxxx0
srshl. */
- return 2563;
+ return 2575;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx10x10xx1xxxx0
srshl. */
- return 2565;
+ return 2577;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1xx01x10xx1xxxx0
srshl. */
- return 2564;
+ return 2576;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx11x10xx1xxxx0
srshl. */
- return 2566;
+ return 2578;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1xx00xx0xx0xxxx1
umax. */
- return 2638;
+ return 2650;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx10xx0xx0xxxx1
umax. */
- return 2640;
+ return 2652;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1xx01xx0xx0xxxx1
umax. */
- return 2639;
+ return 2651;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx11xx0xx0xxxx1
umax. */
- return 2641;
+ return 2653;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1xx00x00xx1xxxx1
umin. */
- return 2642;
+ return 2654;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx10x00xx1xxxx1
umin. */
- return 2644;
+ return 2656;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1xx01x00xx1xxxx1
umin. */
- return 2643;
+ return 2655;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx11x00xx1xxxx1
umin. */
- return 2645;
+ return 2657;
}
}
}
10987654321098765432109876543210
x1000001xx1xxxxx1xx00x10xx1xxxx1
urshl. */
- return 2646;
+ return 2658;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx10x10xx1xxxx1
urshl. */
- return 2648;
+ return 2660;
}
}
else
10987654321098765432109876543210
x1000001xx1xxxxx1xx01x10xx1xxxx1
urshl. */
- return 2647;
+ return 2659;
}
else
{
10987654321098765432109876543210
x1000001xx1xxxxx1xx11x10xx1xxxx1
urshl. */
- return 2649;
+ return 2661;
}
}
}
10987654321098765432109876543210
x0100001001xxxxx000xxxxxxxxx0xxx
st1b. */
- return 2573;
+ return 2585;
}
else
{
10987654321098765432109876543210
x0100001001xxxxx010xxxxxxxxx0xxx
st1w. */
- return 2597;
+ return 2609;
}
}
else
10987654321098765432109876543210
x0100001001xxxxx001xxxxxxxxx0xxx
st1h. */
- return 2589;
+ return 2601;
}
else
{
10987654321098765432109876543210
x0100001001xxxxx011xxxxxxxxx0xxx
st1d. */
- return 2581;
+ return 2593;
}
}
}
10987654321098765432109876543210
x0100001001xxxxx000xxxxxxxxx1xxx
stnt1b. */
- return 2605;
+ return 2617;
}
else
{
10987654321098765432109876543210
x0100001001xxxxx010xxxxxxxxx1xxx
stnt1w. */
- return 2629;
+ return 2641;
}
}
else
10987654321098765432109876543210
x0100001001xxxxx001xxxxxxxxx1xxx
stnt1h. */
- return 2621;
+ return 2633;
}
else
{
10987654321098765432109876543210
x0100001001xxxxx011xxxxxxxxx1xxx
stnt1d. */
- return 2613;
+ return 2625;
}
}
}
10987654321098765432109876543210
x0100001001xxxxx100xxxxxxxxx0xxx
st1b. */
- return 2574;
+ return 2586;
}
else
{
10987654321098765432109876543210
x1100001001xxxxx100xxxxxxxxx0xxx
str. */
- return 2631;
+ return 2643;
}
}
else
10987654321098765432109876543210
xx100001001xxxxx110xxxxxxxxx0xxx
st1w. */
- return 2598;
+ return 2610;
}
}
else
10987654321098765432109876543210
xx100001001xxxxx101xxxxxxxxx0xxx
st1h. */
- return 2590;
+ return 2602;
}
else
{
10987654321098765432109876543210
xx100001001xxxxx111xxxxxxxxx0xxx
st1d. */
- return 2582;
+ return 2594;
}
}
}
10987654321098765432109876543210
xx100001001xxxxx100xxxxxxxxx1xxx
stnt1b. */
- return 2606;
+ return 2618;
}
else
{
10987654321098765432109876543210
xx100001001xxxxx110xxxxxxxxx1xxx
stnt1w. */
- return 2630;
+ return 2642;
}
}
else
10987654321098765432109876543210
xx100001001xxxxx101xxxxxxxxx1xxx
stnt1h. */
- return 2622;
+ return 2634;
}
else
{
10987654321098765432109876543210
xx100001001xxxxx111xxxxxxxxx1xxx
stnt1d. */
- return 2614;
+ return 2626;
}
}
}
10987654321098765432109876543210
xx100001011xxxxx000xxxxxxxxx0xxx
st1b. */
- return 2569;
+ return 2581;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx100xxxxxxxxx0xxx
st1b. */
- return 2570;
+ return 2582;
}
}
else
10987654321098765432109876543210
xx100001011xxxxx010xxxxxxxxx0xxx
st1w. */
- return 2593;
+ return 2605;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx110xxxxxxxxx0xxx
st1w. */
- return 2594;
+ return 2606;
}
}
}
10987654321098765432109876543210
xx100001011xxxxx001xxxxxxxxx0xxx
st1h. */
- return 2585;
+ return 2597;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx101xxxxxxxxx0xxx
st1h. */
- return 2586;
+ return 2598;
}
}
else
10987654321098765432109876543210
xx100001011xxxxx011xxxxxxxxx0xxx
st1d. */
- return 2577;
+ return 2589;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx111xxxxxxxxx0xxx
st1d. */
- return 2578;
+ return 2590;
}
}
}
10987654321098765432109876543210
xx100001011xxxxx000xxxxxxxxx1xxx
stnt1b. */
- return 2601;
+ return 2613;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx100xxxxxxxxx1xxx
stnt1b. */
- return 2602;
+ return 2614;
}
}
else
10987654321098765432109876543210
xx100001011xxxxx010xxxxxxxxx1xxx
stnt1w. */
- return 2625;
+ return 2637;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx110xxxxxxxxx1xxx
stnt1w. */
- return 2626;
+ return 2638;
}
}
}
10987654321098765432109876543210
xx100001011xxxxx001xxxxxxxxx1xxx
stnt1h. */
- return 2617;
+ return 2629;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx101xxxxxxxxx1xxx
stnt1h. */
- return 2618;
+ return 2630;
}
}
else
10987654321098765432109876543210
xx100001011xxxxx011xxxxxxxxx1xxx
stnt1d. */
- return 2609;
+ return 2621;
}
else
{
10987654321098765432109876543210
xx100001011xxxxx111xxxxxxxxx1xxx
stnt1d. */
- return 2610;
+ return 2622;
}
}
}
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2699;
+ return 2715;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2707;
+ return 2723;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2703;
+ return 2719;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2710;
+ return 2726;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0000x1xxxxxxxxxx
cpyfp. */
- return 2759;
+ return 2775;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1000x1xxxxxxxxxx
cpyfprn. */
- return 2765;
+ return 2781;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0100x1xxxxxxxxxx
cpyfpwn. */
- return 2762;
+ return 2778;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1100x1xxxxxxxxxx
cpyfpn. */
- return 2768;
+ return 2784;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0010x1xxxxxxxxxx
cpyfprt. */
- return 2783;
+ return 2799;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1010x1xxxxxxxxxx
cpyfprtrn. */
- return 2789;
+ return 2805;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0110x1xxxxxxxxxx
cpyfprtwn. */
- return 2786;
+ return 2802;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1110x1xxxxxxxxxx
cpyfprtn. */
- return 2792;
+ return 2808;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0001x1xxxxxxxxxx
cpyfpwt. */
- return 2771;
+ return 2787;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1001x1xxxxxxxxxx
cpyfpwtrn. */
- return 2777;
+ return 2793;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0101x1xxxxxxxxxx
cpyfpwtwn. */
- return 2774;
+ return 2790;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1101x1xxxxxxxxxx
cpyfpwtn. */
- return 2780;
+ return 2796;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0011x1xxxxxxxxxx
cpyfpt. */
- return 2795;
+ return 2811;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1011x1xxxxxxxxxx
cpyfptrn. */
- return 2801;
+ return 2817;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0111x1xxxxxxxxxx
cpyfptwn. */
- return 2798;
+ return 2814;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1111x1xxxxxxxxxx
cpyfptn. */
- return 2804;
+ return 2820;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2700;
+ return 2716;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2708;
+ return 2724;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2704;
+ return 2720;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2711;
+ return 2727;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0000x1xxxxxxxxxx
cpyfm. */
- return 2760;
+ return 2776;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1000x1xxxxxxxxxx
cpyfmrn. */
- return 2766;
+ return 2782;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0100x1xxxxxxxxxx
cpyfmwn. */
- return 2763;
+ return 2779;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1100x1xxxxxxxxxx
cpyfmn. */
- return 2769;
+ return 2785;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0010x1xxxxxxxxxx
cpyfmrt. */
- return 2784;
+ return 2800;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1010x1xxxxxxxxxx
cpyfmrtrn. */
- return 2790;
+ return 2806;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0110x1xxxxxxxxxx
cpyfmrtwn. */
- return 2787;
+ return 2803;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1110x1xxxxxxxxxx
cpyfmrtn. */
- return 2793;
+ return 2809;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0001x1xxxxxxxxxx
cpyfmwt. */
- return 2772;
+ return 2788;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1001x1xxxxxxxxxx
cpyfmwtrn. */
- return 2778;
+ return 2794;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0101x1xxxxxxxxxx
cpyfmwtwn. */
- return 2775;
+ return 2791;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1101x1xxxxxxxxxx
cpyfmwtn. */
- return 2781;
+ return 2797;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0011x1xxxxxxxxxx
cpyfmt. */
- return 2796;
+ return 2812;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1011x1xxxxxxxxxx
cpyfmtrn. */
- return 2802;
+ return 2818;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0111x1xxxxxxxxxx
cpyfmtwn. */
- return 2799;
+ return 2815;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1111x1xxxxxxxxxx
cpyfmtn. */
- return 2805;
+ return 2821;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2702;
+ return 2718;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2709;
+ return 2725;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2706;
+ return 2722;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2701;
+ return 2717;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2705;
+ return 2721;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0000x1xxxxxxxxxx
cpyfe. */
- return 2761;
+ return 2777;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0000x1xxxxxxxxxx
setp. */
- return 2855;
+ return 2871;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1000x1xxxxxxxxxx
cpyfern. */
- return 2767;
+ return 2783;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1000x1xxxxxxxxxx
sete. */
- return 2857;
+ return 2873;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0100x1xxxxxxxxxx
cpyfewn. */
- return 2764;
+ return 2780;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0100x1xxxxxxxxxx
setm. */
- return 2856;
+ return 2872;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1100x1xxxxxxxxxx
cpyfen. */
- return 2770;
+ return 2786;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0010x1xxxxxxxxxx
cpyfert. */
- return 2785;
+ return 2801;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0010x1xxxxxxxxxx
setpn. */
- return 2861;
+ return 2877;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1010x1xxxxxxxxxx
cpyfertrn. */
- return 2791;
+ return 2807;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1010x1xxxxxxxxxx
seten. */
- return 2863;
+ return 2879;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0110x1xxxxxxxxxx
cpyfertwn. */
- return 2788;
+ return 2804;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0110x1xxxxxxxxxx
setmn. */
- return 2862;
+ return 2878;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1110x1xxxxxxxxxx
cpyfertn. */
- return 2794;
+ return 2810;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0001x1xxxxxxxxxx
cpyfewt. */
- return 2773;
+ return 2789;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0001x1xxxxxxxxxx
setpt. */
- return 2858;
+ return 2874;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1001x1xxxxxxxxxx
cpyfewtrn. */
- return 2779;
+ return 2795;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1001x1xxxxxxxxxx
setet. */
- return 2860;
+ return 2876;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0101x1xxxxxxxxxx
cpyfewtwn. */
- return 2776;
+ return 2792;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0101x1xxxxxxxxxx
setmt. */
- return 2859;
+ return 2875;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1101x1xxxxxxxxxx
cpyfewtn. */
- return 2782;
+ return 2798;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0011x1xxxxxxxxxx
cpyfet. */
- return 2797;
+ return 2813;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0011x1xxxxxxxxxx
setptn. */
- return 2864;
+ return 2880;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1011x1xxxxxxxxxx
cpyfetrn. */
- return 2803;
+ return 2819;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1011x1xxxxxxxxxx
setetn. */
- return 2866;
+ return 2882;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0111x1xxxxxxxxxx
cpyfetwn. */
- return 2800;
+ return 2816;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0111x1xxxxxxxxxx
setmtn. */
- return 2865;
+ return 2881;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1111x1xxxxxxxxxx
cpyfetn. */
- return 2806;
+ return 2822;
}
}
}
10987654321098765432109876543210
x1x11010110xxxx0x01000xxxxxxxxxx
abs. */
- return 2884;
+ return 2900;
}
else
{
10987654321098765432109876543210
xxx11010110xxxxxx11000xxxxxxxxxx
smax. */
- return 2887;
+ return 2903;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2697;
+ return 2713;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2698;
+ return 2714;
}
}
else
10987654321098765432109876543210
xxx11010110xxxxxx11010xxxxxxxxxx
smin. */
- return 2889;
+ return 2905;
}
}
}
10987654321098765432109876543210
xxx11010110xxxx0x00110xxxxxxxxxx
ctz. */
- return 2886;
+ return 2902;
}
else
{
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2696;
+ return 2712;
}
else
{
10987654321098765432109876543210
xxx11010x10xxxxxx11001xxxxxxxxxx
umax. */
- return 2888;
+ return 2904;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxxxx11011xxxxxxxxxx
umin. */
- return 2890;
+ return 2906;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxx0x00111xxxxxxxxxx
cnt. */
- return 2885;
+ return 2901;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2716;
+ return 2732;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2717;
+ return 2733;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2715;
+ return 2731;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2744;
+ return 2760;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2720;
+ return 2736;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2721;
+ return 2737;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2741;
+ return 2757;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2748;
+ return 2764;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2747;
+ return 2763;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2740;
+ return 2756;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2746;
+ return 2762;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2745;
+ return 2761;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2724;
+ return 2740;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2725;
+ return 2741;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2718;
+ return 2734;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2742;
+ return 2758;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2719;
+ return 2735;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2728;
+ return 2744;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2730;
+ return 2746;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2732;
+ return 2748;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2729;
+ return 2745;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2731;
+ return 2747;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2733;
+ return 2749;
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2712;
+ return 2728;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2714;
+ return 2730;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2713;
+ return 2729;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2722;
+ return 2738;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2723;
+ return 2739;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2726;
+ return 2742;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2727;
+ return 2743;
}
}
}
10987654321098765432109876543210
001001x1xx1xxxxx01x000xxxxx10xxx
whilege. */
- return 2650;
+ return 2662;
}
else
{
10987654321098765432109876543210
001001x1xx1xxxxx01x000xxxxx11xxx
whilegt. */
- return 2651;
+ return 2663;
}
}
else
10987654321098765432109876543210
001001x1xx1xxxxx011100xxxxx1xxxx
pext. */
- return 2546;
+ return 2558;
}
}
}
10987654321098765432109876543210
001001x1xx1xxxxx01x010xxxxx10xxx
whilehs. */
- return 2653;
+ return 2665;
}
else
{
10987654321098765432109876543210
001001x1xx1xxxxx01x010xxxxx11xxx
whilehi. */
- return 2652;
+ return 2664;
}
}
else
10987654321098765432109876543210
001001x1xx1xxxxx011110xxxxx1xxxx
ptrue. */
- return 2548;
+ return 2560;
}
}
}
10987654321098765432109876543210
001001x1xx1xxxxx01x001xxxxx10xxx
whilelt. */
- return 2657;
+ return 2669;
}
else
{
10987654321098765432109876543210
001001x1xx1xxxxx01x001xxxxx11xxx
whilele. */
- return 2654;
+ return 2666;
}
}
else
10987654321098765432109876543210
001001x1xx1xxxxx011101xxxxx1xxxx
pext. */
- return 2547;
+ return 2559;
}
}
}
10987654321098765432109876543210
001001x1xx1xxxxx01x011xxxxx10xxx
whilelo. */
- return 2655;
+ return 2667;
}
else
{
10987654321098765432109876543210
001001x1xx1xxxxx01x011xxxxx11xxx
whilels. */
- return 2656;
+ return 2668;
}
}
else
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2743;
+ return 2759;
}
}
else
10987654321098765432109876543210
x1010100xxxxxxxxxxxxxxxxxxx1xxxx
bc.c. */
- return 2879;
+ return 2895;
}
else
{
10987654321098765432109876543210
xx01110100xxxxxx0000xxxxxxxxxxxx
cpyp. */
- return 2807;
+ return 2823;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0000xxxxxxxxxxxx
cpye. */
- return 2809;
+ return 2825;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1000xxxxxxxxxxxx
cpyprn. */
- return 2813;
+ return 2829;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1000xxxxxxxxxxxx
cpyern. */
- return 2815;
+ return 2831;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0100xxxxxxxxxxxx
cpypwn. */
- return 2810;
+ return 2826;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0100xxxxxxxxxxxx
cpyewn. */
- return 2812;
+ return 2828;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1100xxxxxxxxxxxx
cpypn. */
- return 2816;
+ return 2832;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1100xxxxxxxxxxxx
cpyen. */
- return 2818;
+ return 2834;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0010xxxxxxxxxxxx
cpyprt. */
- return 2831;
+ return 2847;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0010xxxxxxxxxxxx
cpyert. */
- return 2833;
+ return 2849;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1010xxxxxxxxxxxx
cpyprtrn. */
- return 2837;
+ return 2853;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1010xxxxxxxxxxxx
cpyertrn. */
- return 2839;
+ return 2855;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0110xxxxxxxxxxxx
cpyprtwn. */
- return 2834;
+ return 2850;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0110xxxxxxxxxxxx
cpyertwn. */
- return 2836;
+ return 2852;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1110xxxxxxxxxxxx
cpyprtn. */
- return 2840;
+ return 2856;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1110xxxxxxxxxxxx
cpyertn. */
- return 2842;
+ return 2858;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0001xxxxxxxxxxxx
cpypwt. */
- return 2819;
+ return 2835;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0001xxxxxxxxxxxx
cpyewt. */
- return 2821;
+ return 2837;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1001xxxxxxxxxxxx
cpypwtrn. */
- return 2825;
+ return 2841;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1001xxxxxxxxxxxx
cpyewtrn. */
- return 2827;
+ return 2843;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0101xxxxxxxxxxxx
cpypwtwn. */
- return 2822;
+ return 2838;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0101xxxxxxxxxxxx
cpyewtwn. */
- return 2824;
+ return 2840;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1101xxxxxxxxxxxx
cpypwtn. */
- return 2828;
+ return 2844;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1101xxxxxxxxxxxx
cpyewtn. */
- return 2830;
+ return 2846;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0011xxxxxxxxxxxx
cpypt. */
- return 2843;
+ return 2859;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0011xxxxxxxxxxxx
cpyet. */
- return 2845;
+ return 2861;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1011xxxxxxxxxxxx
cpyptrn. */
- return 2849;
+ return 2865;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1011xxxxxxxxxxxx
cpyetrn. */
- return 2851;
+ return 2867;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0111xxxxxxxxxxxx
cpyptwn. */
- return 2846;
+ return 2862;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0111xxxxxxxxxxxx
cpyetwn. */
- return 2848;
+ return 2864;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1111xxxxxxxxxxxx
cpyptn. */
- return 2852;
+ return 2868;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1111xxxxxxxxxxxx
cpyetn. */
- return 2854;
+ return 2870;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0000xxxxxxxxxxxx
cpym. */
- return 2808;
+ return 2824;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0000xxxxxxxxxxxx
setgp. */
- return 2867;
+ return 2883;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1000xxxxxxxxxxxx
cpymrn. */
- return 2814;
+ return 2830;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1000xxxxxxxxxxxx
setge. */
- return 2869;
+ return 2885;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0100xxxxxxxxxxxx
cpymwn. */
- return 2811;
+ return 2827;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0100xxxxxxxxxxxx
setgm. */
- return 2868;
+ return 2884;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1100xxxxxxxxxxxx
cpymn. */
- return 2817;
+ return 2833;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0010xxxxxxxxxxxx
cpymrt. */
- return 2832;
+ return 2848;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0010xxxxxxxxxxxx
setgpn. */
- return 2873;
+ return 2889;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1010xxxxxxxxxxxx
cpymrtrn. */
- return 2838;
+ return 2854;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1010xxxxxxxxxxxx
setgen. */
- return 2875;
+ return 2891;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0110xxxxxxxxxxxx
cpymrtwn. */
- return 2835;
+ return 2851;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0110xxxxxxxxxxxx
setgmn. */
- return 2874;
+ return 2890;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1110xxxxxxxxxxxx
cpymrtn. */
- return 2841;
+ return 2857;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0001xxxxxxxxxxxx
cpymwt. */
- return 2820;
+ return 2836;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0001xxxxxxxxxxxx
setgpt. */
- return 2870;
+ return 2886;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1001xxxxxxxxxxxx
cpymwtrn. */
- return 2826;
+ return 2842;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1001xxxxxxxxxxxx
setget. */
- return 2872;
+ return 2888;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0101xxxxxxxxxxxx
cpymwtwn. */
- return 2823;
+ return 2839;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0101xxxxxxxxxxxx
setgmt. */
- return 2871;
+ return 2887;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1101xxxxxxxxxxxx
cpymwtn. */
- return 2829;
+ return 2845;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0011xxxxxxxxxxxx
cpymt. */
- return 2844;
+ return 2860;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0011xxxxxxxxxxxx
setgptn. */
- return 2876;
+ return 2892;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1011xxxxxxxxxxxx
cpymtrn. */
- return 2850;
+ return 2866;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1011xxxxxxxxxxxx
setgetn. */
- return 2878;
+ return 2894;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0111xxxxxxxxxxxx
cpymtwn. */
- return 2847;
+ return 2863;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0111xxxxxxxxxxxx
setgmtn. */
- return 2877;
+ return 2893;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1111xxxxxxxxxxxx
cpymtn. */
- return 2853;
+ return 2869;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2734;
+ return 2750;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2660;
+ return 2676;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2736;
+ return 2752;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2737;
+ return 2753;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2667;
+ return 2683;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2669;
+ return 2685;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2671;
+ return 2687;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2672;
+ return 2688;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2665;
+ return 2681;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2674;
+ return 2690;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2673;
+ return 2689;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2678;
+ return 2694;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2675;
+ return 2691;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2659;
+ return 2675;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2735;
+ return 2751;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2751;
+ return 2767;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2749;
+ return 2765;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2756;
+ return 2772;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2755;
+ return 2771;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2752;
+ return 2768;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2753;
+ return 2769;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2670;
+ return 2686;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2663;
+ return 2679;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2676;
+ return 2692;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2666;
+ return 2682;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2679;
+ return 2695;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2664;
+ return 2680;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2677;
+ return 2693;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2668;
+ return 2684;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2682;
+ return 2698;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2686;
+ return 2702;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2683;
+ return 2699;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2687;
+ return 2703;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2680;
+ return 2696;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2684;
+ return 2700;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2681;
+ return 2697;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2685;
+ return 2701;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2688;
+ return 2704;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2692;
+ return 2708;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2689;
+ return 2705;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2693;
+ return 2709;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2690;
+ return 2706;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2694;
+ return 2710;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2691;
+ return 2707;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2695;
+ return 2711;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2662;
+ return 2678;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2661;
+ return 2677;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2739;
+ return 2755;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2738;
+ return 2754;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2750;
+ return 2766;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2758;
+ return 2774;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2757;
+ return 2773;
}
}
}
case 2391: return NULL; /* mova --> NULL. */
case 2388: value = 2390; break; /* mov --> mova. */
case 2390: return NULL; /* mova --> NULL. */
- case 2534: value = 2542; break; /* mov --> mova. */
- case 2542: return NULL; /* mova --> NULL. */
- case 2530: value = 2538; break; /* mov --> mova. */
- case 2538: return NULL; /* mova --> NULL. */
- case 2532: value = 2540; break; /* mov --> mova. */
- case 2540: return NULL; /* mova --> NULL. */
- case 2528: value = 2536; break; /* mov --> mova. */
- case 2536: return NULL; /* mova --> NULL. */
- case 2535: value = 2543; break; /* mov --> mova. */
- case 2543: return NULL; /* mova --> NULL. */
- case 2531: value = 2539; break; /* mov --> mova. */
- case 2539: return NULL; /* mova --> NULL. */
- case 2533: value = 2541; break; /* mov --> mova. */
- case 2541: return NULL; /* mova --> NULL. */
- case 2529: value = 2537; break; /* mov --> mova. */
- case 2537: return NULL; /* mova --> NULL. */
+ case 2546: value = 2554; break; /* mov --> mova. */
+ case 2554: return NULL; /* mova --> NULL. */
+ case 2542: value = 2550; break; /* mov --> mova. */
+ case 2550: return NULL; /* mova --> NULL. */
+ case 2544: value = 2552; break; /* mov --> mova. */
+ case 2552: return NULL; /* mova --> NULL. */
+ case 2540: value = 2548; break; /* mov --> mova. */
+ case 2548: return NULL; /* mova --> NULL. */
+ case 2547: value = 2555; break; /* mov --> mova. */
+ case 2555: return NULL; /* mova --> NULL. */
+ case 2543: value = 2551; break; /* mov --> mova. */
+ case 2551: return NULL; /* mova --> NULL. */
+ case 2545: value = 2553; break; /* mov --> mova. */
+ case 2553: return NULL; /* mova --> NULL. */
+ case 2541: value = 2549; break; /* mov --> mova. */
+ case 2549: return NULL; /* mova --> NULL. */
case 2393: value = 2398; break; /* ld1b --> ld1b. */
case 2398: return NULL; /* ld1b --> NULL. */
case 2395: value = 2400; break; /* ld1w --> ld1w. */
case 2407: value = 2412; break; /* st1q --> st1q. */
case 2412: return NULL; /* st1q --> NULL. */
case 12: value = 19; break; /* add --> addg. */
- case 19: value = 2880; break; /* addg --> smax. */
- case 2880: value = 2881; break; /* smax --> umax. */
- case 2881: value = 2882; break; /* umax --> smin. */
- case 2882: value = 2883; break; /* smin --> umin. */
- case 2883: return NULL; /* umin --> NULL. */
+ case 19: value = 2896; break; /* addg --> smax. */
+ case 2896: value = 2897; break; /* smax --> umax. */
+ case 2897: value = 2898; break; /* umax --> smin. */
+ case 2898: value = 2899; break; /* smin --> umin. */
+ case 2899: return NULL; /* umin --> NULL. */
case 16: value = 20; break; /* sub --> subg. */
case 20: return NULL; /* subg --> NULL. */
case 971: value = 975; break; /* stnp --> stp. */
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2754; break; /* fcvt --> bfcvt. */
- case 2754: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2770; break; /* fcvt --> bfcvt. */
+ case 2770: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 33:
case 34:
case 35:
- case 257:
+ case 259:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 193:
case 194:
case 237:
- case 251:
- case 252:
+ case 253:
case 254:
case 256:
- case 261:
- case 262:
+ case 258:
+ case 263:
+ case 264:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
case 107:
return aarch64_ext_prfop (self, info, code, inst, errors);
case 108:
- case 253:
case 255:
+ case 257:
return aarch64_ext_none (self, info, code, inst, errors);
case 109:
return aarch64_ext_hint (self, info, code, inst, errors);
case 248:
case 249:
case 250:
+ case 251:
+ case 252:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 239:
case 240:
return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 244:
return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
- case 258:
- case 259:
case 260:
+ case 261:
+ case 262:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"},
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
{ 21, 2 }, /* hw: in move wide constant instructions. */
{ 8, 1 }, /* imm1_8: general immediate in bits [8]. */
+ { 10, 1 }, /* imm1_10: general immediate in bits [10]. */
{ 16, 1 }, /* imm1_16: general immediate in bits [16]. */
{ 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
+ { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */
{ 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */
{ 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
return 0;
break;
+ case AARCH64_OPND_SME_Zm_INDEX1:
+ case AARCH64_OPND_SME_Zm_INDEX2:
+ size = get_operand_fields_width (get_operand_from_code (type)) - 4;
+ if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
+ 0, (1 << size) - 1))
+ return 0;
+ break;
+
case AARCH64_OPND_SME_Zm:
if (opnd->reg.regno > 15)
{
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
+ case AARCH64_OPND_SME_Zm_INDEX1:
+ case AARCH64_OPND_SME_Zm_INDEX2:
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
case AARCH64_OPND_SME_Zn_INDEX2_16:
FLD_defgh,
FLD_hw,
FLD_imm1_8,
+ FLD_imm1_10,
FLD_imm1_16,
FLD_imm2_8,
+ FLD_imm2_10,
FLD_imm2_15,
FLD_imm2_16,
FLD_imm3_0,
static const aarch64_feature_set aarch64_feature_sme2 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
| AARCH64_FEATURE_SME2, 0);
+static const aarch64_feature_set aarch64_feature_sme2_f64f64 =
+ AARCH64_FEATURE (AARCH64_FEATURE_SME2 | AARCH64_FEATURE_SME_F64F64, 0);
static const aarch64_feature_set aarch64_feature_v8_6 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
static const aarch64_feature_set aarch64_feature_v8_7 =
#define SME_F64F64 &aarch64_feature_sme_f64f64
#define SME_I16I64 &aarch64_feature_sme_i16i64
#define SME2 &aarch64_feature_sme2
+#define SME2_F64F64 &aarch64_feature_sme2_f64f64
#define ARMV8_6 &aarch64_feature_v8_6
#define ARMV8_6_SVE &aarch64_feature_v8_6
#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
#define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \
F_STRICT | FLAGS, 0, TIED, NULL }
+#define SME2_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SME2_F64F64, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
SME2_INSN ("fminnm", 0xc120a921, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
SME2_INSN ("fminnm", 0xc120b121, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1),
SME2_INSN ("fminnm", 0xc120b921, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1),
+ SME2_INSN ("fmla", 0xc1500000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0),
+ SME2_INSN ("fmla", 0xc1508000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0),
+ SME2_INSN ("fmla", 0xc1201800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),
+ SME2_INSN ("fmla", 0xc1301800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
+ SME2_INSN ("fmla", 0xc1a01800, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
+ SME2_INSN ("fmla", 0xc1a11800, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
+ SME2_INSN ("fmls", 0xc1500010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0),
+ SME2_INSN ("fmls", 0xc1508010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0),
+ SME2_INSN ("fmls", 0xc1201808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),
+ SME2_INSN ("fmls", 0xc1301808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
+ SME2_INSN ("fmls", 0xc1a01808, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
+ SME2_INSN ("fmls", 0xc1a11808, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0),
+ /* SME2 F64F64 instructions. */
+ SME2_F64F64_INSN ("fmla", 0xc1d00000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0),
+ SME2_F64F64_INSN ("fmla", 0xc1d08000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),
+ SME2_F64F64_INSN ("fmls", 0xc1d00010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0),
+ SME2_F64F64_INSN ("fmls", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),
+
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
"Source scalable predicate register with index ") \
+ Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \
+ F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \
+ F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \
F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \