run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
- log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
+
+ log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n",
active_design->scratchpad_get_int("write_xaiger.num_ands"),
active_design->scratchpad_get_int("write_xaiger.num_wires"),
+ log_id(mod),
active_design->scratchpad_get_int("write_xaiger.num_inputs"),
num_outputs);
if (num_outputs) {
std::string wire_delay, std::string tempdir_name
)
{
- //FIXME:
- //log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
- // module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
-
std::string abc9_script;
if (!lut_costs.empty())