MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a

The MMI instruction set has been implemented in many Loongson
processors.  There is a lot of software optimized for MMI.  This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.

2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
            Maciej W. Rozycki  <macro@mips.com>

bfd/
	* elfxx-mips.c (print_mips_ases): Add MMI extension.

binutils/
	* readelf.c (print_mips_ases): Add MMI extension.

gas/
	* NEWS: Mention MultiMedia extensions Instructions (MMI)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
	OPTION_NO_LOONGSON_MMI.
	(md_longopts): Likewise.
	(mips_ases): Define availability for MMI.
	(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
	AFL_ASE_LOONGSON_MMI.
	(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
	(md_show_usage): Add help for -mloongson-mmi and
	-mno-loongson-mmi.
	* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
	* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
	.set loongson-mmi and .set noloongson-mmi.
	* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.s: Here.
	* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.s: Here.
	* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
	loongson-3a-mmi tests.

include/
	* elf/mips.h (AFL_ASE_MMI): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
	* opcode/mips.h (ASE_LOONGSON_MMI): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
	loongson3a descriptors.
	(parse_mips_ase_option): Handle -M loongson-mmi option.
	(print_mips_disassembler_options): Document -M loongson-mmi.
	* mips-opc.c (LMMI): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
	instructions.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 9b7048c60014e5ba4afd4789f7423e55c0c645d2..d8bbbf5a0406eaf86a002fad890a46b8a2616e5d 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+           Maciej W. Rozycki  <macro@mips.com>
+
+       * elfxx-mips.c (print_mips_ases): Add MMI extension.
+
 2018-07-20  Maciej W. Rozycki  <macro@mips.com>
 
        * elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Do not

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index cc767ea6bf9b232f8d4cdc133f184ea6b5e37f29..e538fd14615411d372a59ec7ae4fbff6a84e02fe 100644 (file)
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -15675,6 +15675,8 @@ print_mips_ases (FILE *file, unsigned int mask)
     fputs ("\n\tCRC ASE", file);
   if (mask & AFL_ASE_GINV)
     fputs ("\n\tGINV ASE", file);
+  if (mask & AFL_ASE_LOONGSON_MMI)
+    fputs ("\n\tLoongson MMI ASE", file);
   if (mask == 0)
     fprintf (file, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 62a040c84a61a01e02c7840c03277499126d727c..df05bc04f913de3b2e9310a73b5234cd8b0916a9 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+           Maciej W. Rozycki  <macro@mips.com>
+
+       * readelf.c (print_mips_ases): Add MMI extension.
+
 2018-07-19  DJ Delorie  <dj@redhat.com>
 
        * MAINTAINERS (RL78, RX): Remove myself as maintainer.

diff --git a/binutils/readelf.c b/binutils/readelf.c
index 2b78db219b9c951fbbb8d81a0fed23bdbfb3e996..63d3453ea18580748d3c50fc3bd070acfdff6f21 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -15583,6 +15583,8 @@ print_mips_ases (unsigned int mask)
     fputs ("\n\tCRC ASE", stdout);
   if (mask & AFL_ASE_GINV)
     fputs ("\n\tGINV ASE", stdout);
+  if (mask & AFL_ASE_LOONGSON_MMI)
+    fputs ("\n\tLoongson MMI ASE", stdout);
   if (mask == 0)
     fprintf (stdout, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index beea270247a6e52ced6306b577628bddf94e28f5..a612f71b43c94e3f5d2d3c9b83a733184c24f8ab 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,33 @@
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+           Maciej W. Rozycki  <macro@mips.com>
+
+       * NEWS: Mention MultiMedia extensions Instructions (MMI)
+       support.
+       * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
+       OPTION_NO_LOONGSON_MMI.
+       (md_longopts): Likewise.
+       (mips_ases): Define availability for MMI.
+       (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
+       AFL_ASE_LOONGSON_MMI.
+       (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
+       (md_show_usage): Add help for -mloongson-mmi and
+       -mno-loongson-mmi.
+       * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
+       * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
+       .set loongson-mmi and .set noloongson-mmi.
+       * testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
+       * testsuite/gas/mips/loongson-2f-mmi.d: Here.  Add ISA/ASE
+       flag verification.
+       * testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
+       * testsuite/gas/mips/loongson-2f-mmi.s: Here.
+       * testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
+       * testsuite/gas/mips/loongson-3a-mmi.d: Here.  Add ISA/ASE
+       flag verification.
+       * testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
+       * testsuite/gas/mips/loongson-3a-mmi.s: Here.
+       * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
+       loongson-3a-mmi tests.
+
 2018-07-20  Jose E. Marchesi  <jose.marchesi@oracle.com>
            Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 

diff --git a/gas/NEWS b/gas/NEWS
index 5fd844cdc4cca9b6bfb0c9452c37789a685ea5c9..c7d9332e23a075571a2830210d5e9f8749c464d2 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
 -*- text -*-
 
+* Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI)
+  ASE.
+
 Changes in 2.31:
 
 * The ADR and ADRL pseudo-instructions supported by the ARM assembler

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 59df78715537308169da7de0528bdfdc8fbb5a95..9bbf59cca6561286b068a78e3f5224ee0d925429 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1529,6 +1529,8 @@ enum options
     OPTION_NO_ODD_SPREG,
     OPTION_GINV,
     OPTION_NO_GINV,
+    OPTION_LOONGSON_MMI,
+    OPTION_NO_LOONGSON_MMI,
     OPTION_END_OF_ENUM
   };
 
@@ -1589,6 +1591,8 @@ struct option md_longopts[] =
   {"mno-crc", no_argument, NULL, OPTION_NO_CRC},
   {"mginv", no_argument, NULL, OPTION_GINV},
   {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
+  {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
+  {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
 
   /* Old-style architecture options.  Don't add more of these.  */
   {"m4650", no_argument, NULL, OPTION_M4650},
@@ -1786,6 +1790,11 @@ static const struct mips_ase mips_ases[] = {
     OPTION_GINV, OPTION_NO_GINV,
     6,  6, 6, 6,
     -1 },
+
+  { "loongson-mmi", ASE_LOONGSON_MMI, 0,
+    OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
+    0, 0, -1, -1,
+    -1 },
 };
 
 /* The set of ASEs that require -mfp64.  */
@@ -19017,6 +19026,8 @@ mips_convert_ase_flags (int ase)
     ext_ases |= AFL_ASE_CRC;
   if (ase & ASE_GINV)
     ext_ases |= AFL_ASE_GINV;
+  if (ase & ASE_LOONGSON_MMI)
+    ext_ases |= AFL_ASE_LOONGSON_MMI;
 
   return ext_ases;
 }
@@ -19663,7 +19674,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "r5900",          0, 0,                    ISA_MIPS3,    CPU_R5900 },
   /* ST Microelectronics Loongson 2E and 2F cores */
   { "loongson2e",     0, 0,                    ISA_MIPS3,    CPU_LOONGSON_2E },
-  { "loongson2f",     0, 0,                    ISA_MIPS3,    CPU_LOONGSON_2F },
+  { "loongson2f",     0, ASE_LOONGSON_MMI,     ISA_MIPS3,    CPU_LOONGSON_2F },
 
   /* MIPS IV */
   { "r8000",          0, 0,                    ISA_MIPS4,    CPU_R8000 },
@@ -19762,7 +19773,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   /* Broadcom SB-1A CPU core */
   { "sb1a",           0, ASE_MIPS3D | ASE_MDMX,        ISA_MIPS64,   CPU_SB1 },
 
-  { "loongson3a",     0, 0,                    ISA_MIPS64R2, CPU_LOONGSON_3A },
+  { "loongson3a",     0, ASE_LOONGSON_MMI,     ISA_MIPS64R2, CPU_LOONGSON_3A },
 
   /* MIPS 64 Release 2 */
 
@@ -20037,6 +20048,9 @@ MIPS options:\n\
 -mginv                 generate Global INValidate (GINV) instructions\n\
 -mno-ginv              do not generate Global INValidate instructions\n"));
   fprintf (stream, _("\
+-mloongson-mmi         generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
+-mno-loongson-mmi      do not generate Loongson MultiMedia extensions Instructions\n"));
+  fprintf (stream, _("\
 -minsn32               only generate 32-bit microMIPS instructions\n\
 -mno-insn32            generate all microMIPS instructions\n"));
   fprintf (stream, _("\

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 49b1ef1b8b8cc1b1386b3c431c635bfc2eb7fda3..e9b6016aaa42ec89cc12c224d8e74e02f32041db 100644 (file)
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -424,6 +424,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mmcu}] [@b{-mno-mcu}]
    [@b{-mcrc}] [@b{-mno-crc}]
    [@b{-mginv}] [@b{-mno-ginv}]
+   [@b{-mloongson-mmi}] [@b{-mno-loongson-mmi}]
    [@b{-minsn32}] [@b{-mno-insn32}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
@@ -1526,6 +1527,13 @@ Generate code for the Global INValidate (GINV) Application Specific
 Extension.  This tells the assembler to accept GINV instructions.
 @samp{-mno-ginv} turns off this option.
 
+@item -mloongson-mmi
+@itemx -mno-loongson-mmi
+Generate code for the Loongson MultiMedia extensions Instructions (MMI)
+Application Specific Extension.  This tells the assembler to accept MMI
+instructions.
+@samp{-mno-loongson-mmi} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 24f68433d21640fc2099e50b3ebe63ae385a2722..d10f2d6439f864a64dd21a4931d192ec4ff877d4 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -246,6 +246,13 @@ Generate code for the Global INValidate (GINV) Application Specific
 Extension.  This tells the assembler to accept GINV instructions.
 @samp{-mno-ginv} turns off this option.
 
+@item -mloongson-mmi
+@itemx -mno-loongson-mmi
+Generate code for the Loongson MultiMedia extensions Instructions (MMI)
+Application Specific Extension.  This tells the assembler to accept MMI
+instructions.
+@samp{-mno-loongson-mmi} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the
@@ -1137,6 +1144,14 @@ The directive @code{.set ginv} makes the assembler accept instructions
 from the GINV Extension from that point on in the assembly.  The
 @code{.set noginv} directive prevents GINV instructions from being accepted.
 
+@cindex Loongson MultiMedia extensions Instructions (MMI) generation override
+@kindex @code{.set loongson-mmi}
+@kindex @code{.set noloongson-mmi}
+The directive @code{.set loongson-mmi} makes the assembler accept
+instructions from the MMI Extension from that point on in the assembly.
+The @code{.set noloongson-mmi} directive prevents MMI instructions from
+being accepted.
+
 Traditional MIPS assemblers do not support these directives.
 
 @node MIPS Floating-Point

diff --git a/gas/testsuite/gas/mips/loongson-2f-mmi.d b/gas/testsuite/gas/mips/loongson-2f-mmi.d
new file mode 100644 (file)
index 0000000..84224f9
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-2f-mmi.d
@@ -0,0 +1,106 @@
+#as: -march=loongson2f -mabi=o64
+#objdump: -M reg-names=numeric -dp
+#name: Loongson-2F MMI tests
+
+.*:     file format .*
+
+private flags = .*
+
+MIPS ABI Flags Version: 0
+ISA: .*
+GPR size: .*
+CPR1 size: .*
+CPR2 size: .*
+FP ABI: .*
+ISA Extension: ST Microelectronics Loongson 2F
+ASEs:
+       Loongson MMI ASE
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <simd_insns>:
+.*:    4b420802        packsshb        \$f0,\$f1,\$f2
+.*:    4b2520c2        packsswh        \$f3,\$f4,\$f5
+.*:    4b683982        packushb        \$f6,\$f7,\$f8
+.*:    4bcb5240        paddb   \$f9,\$f10,\$f11
+.*:    4b4e6b00        paddh   \$f12,\$f13,\$f14
+.*:    4b7183c0        paddw   \$f15,\$f16,\$f17
+.*:    4bf49c80        paddd   \$f18,\$f19,\$f20
+.*:    4b97b540        paddsb  \$f21,\$f22,\$f23
+.*:    4b1ace00        paddsh  \$f24,\$f25,\$f26
+.*:    4bbde6c0        paddusb \$f27,\$f28,\$f29
+.*:    4b220800        paddush \$f0,\$f1,\$f2
+.*:    4be520c2        pandn   \$f3,\$f4,\$f5
+.*:    4b283988        pavgb   \$f6,\$f7,\$f8
+.*:    4b0b5248        pavgh   \$f9,\$f10,\$f11
+.*:    4b8e6b09        pcmpeqb \$f12,\$f13,\$f14
+.*:    4b5183c9        pcmpeqh \$f15,\$f16,\$f17
+.*:    4b149c89        pcmpeqw \$f18,\$f19,\$f20
+.*:    4bb7b549        pcmpgtb \$f21,\$f22,\$f23
+.*:    4b7ace09        pcmpgth \$f24,\$f25,\$f26
+.*:    4b3de6c9        pcmpgtw \$f27,\$f28,\$f29
+.*:    4b42080e        pextrh  \$f0,\$f1,\$f2
+.*:    4b8520c3        pinsrh_0        \$f3,\$f4,\$f5
+.*:    4ba83983        pinsrh_1        \$f6,\$f7,\$f8
+.*:    4bcb5243        pinsrh_2        \$f9,\$f10,\$f11
+.*:    4bee6b03        pinsrh_3        \$f12,\$f13,\$f14
+.*:    4b7183ce        pmaddhw \$f15,\$f16,\$f17
+.*:    4b549c88        pmaxsh  \$f18,\$f19,\$f20
+.*:    4b97b548        pmaxub  \$f21,\$f22,\$f23
+.*:    4b7ace08        pminsh  \$f24,\$f25,\$f26
+.*:    4bbde6c8        pminub  \$f27,\$f28,\$f29
+.*:    4ba0080f        pmovmskb        \$f0,\$f1
+.*:    4ba4188a        pmulhuh \$f2,\$f3,\$f4
+.*:    4b67314a        pmulhh  \$f5,\$f6,\$f7
+.*:    4b4a4a0a        pmullh  \$f8,\$f9,\$f10
+.*:    4b8d62ca        pmuluw  \$f11,\$f12,\$f13
+.*:    4b307b8d        pasubub \$f14,\$f15,\$f16
+.*:    4b80944f        biadd   \$f17,\$f18
+.*:    4b15a4c2        pshufh  \$f19,\$f20,\$f21
+.*:    4b38bd8a        psllh   \$f22,\$f23,\$f24
+.*:    4b1bd64a        psllw   \$f25,\$f26,\$f27
+.*:    4b7eef0b        psrah   \$f28,\$f29,\$f30
+.*:    4b42080b        psraw   \$f0,\$f1,\$f2
+.*:    4b2520cb        psrlh   \$f3,\$f4,\$f5
+.*:    4b08398b        psrlw   \$f6,\$f7,\$f8
+.*:    4bcb5241        psubb   \$f9,\$f10,\$f11
+.*:    4b4e6b01        psubh   \$f12,\$f13,\$f14
+.*:    4b7183c1        psubw   \$f15,\$f16,\$f17
+.*:    4bf49c81        psubd   \$f18,\$f19,\$f20
+.*:    4b97b541        psubsb  \$f21,\$f22,\$f23
+.*:    4b1ace01        psubsh  \$f24,\$f25,\$f26
+.*:    4bbde6c1        psubusb \$f27,\$f28,\$f29
+.*:    4b220801        psubush \$f0,\$f1,\$f2
+.*:    4b6520c3        punpckhbh       \$f3,\$f4,\$f5
+.*:    4b283983        punpckhhw       \$f6,\$f7,\$f8
+.*:    4bab524b        punpckhwd       \$f9,\$f10,\$f11
+.*:    4b4e6b03        punpcklbh       \$f12,\$f13,\$f14
+.*:    4b1183c3        punpcklhw       \$f15,\$f16,\$f17
+.*:    4b949c8b        punpcklwd       \$f18,\$f19,\$f20
+
+[0-9a-f]+ <fixed_point_insns>:
+.*:    4b42080c        add     \$f0,\$f1,\$f2
+.*:    4b0520cc        addu    \$f3,\$f4,\$f5
+.*:    4b68398c        dadd    \$f6,\$f7,\$f8
+.*:    4b4b524d        sub     \$f9,\$f10,\$f11
+.*:    4b0e6b0d        subu    \$f12,\$f13,\$f14
+.*:    4b7183cd        dsub    \$f15,\$f16,\$f17
+.*:    4b349c8c        or      \$f18,\$f19,\$f20
+.*:    4b17b54e        sll     \$f21,\$f22,\$f23
+.*:    4b3ace0e        dsll    \$f24,\$f25,\$f26
+.*:    4b9de6c2        xor     \$f27,\$f28,\$f29
+.*:    4ba20802        nor     \$f0,\$f1,\$f2
+.*:    4bc520c2        and     \$f3,\$f4,\$f5
+.*:    4b08398f        srl     \$f6,\$f7,\$f8
+.*:    4b2b524f        dsrl    \$f9,\$f10,\$f11
+.*:    4b4e6b0f        sra     \$f12,\$f13,\$f14
+.*:    4b7183cf        dsra    \$f15,\$f16,\$f17
+.*:    4b93900c        sequ    \$f18,\$f19
+.*:    4b95a00d        sltu    \$f20,\$f21
+.*:    4b97b00e        sleu    \$f22,\$f23
+.*:    4bb9c00c        seq     \$f24,\$f25
+.*:    4bbbd00d        slt     \$f26,\$f27
+.*:    4bbde00e        sle     \$f28,\$f29
+#pass

diff --git a/gas/testsuite/gas/mips/loongson-2f-mmi.s b/gas/testsuite/gas/mips/loongson-2f-mmi.s
new file mode 100644 (file)
index 0000000..e87d66e
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-2f-mmi.s
@@ -0,0 +1,86 @@
+       .text
+       .set noreorder
+
+simd_insns:
+       packsshb        $f0, $f1, $f2
+       packsswh        $f3, $f4, $f5
+       packushb        $f6, $f7, $f8
+       paddb           $f9, $f10, $f11
+       paddh           $f12, $f13, $f14
+       paddw           $f15, $f16, $f17
+       paddd           $f18, $f19, $f20
+       paddsb          $f21, $f22, $f23
+       paddsh          $f24, $f25, $f26
+       paddusb         $f27, $f28, $f29
+       paddush         $f0, $f1, $f2
+       pandn           $f3, $f4, $f5
+       pavgb           $f6, $f7, $f8
+       pavgh           $f9, $f10, $f11
+       pcmpeqb         $f12, $f13, $f14
+       pcmpeqh         $f15, $f16, $f17
+       pcmpeqw         $f18, $f19, $f20
+       pcmpgtb         $f21, $f22, $f23
+       pcmpgth         $f24, $f25, $f26
+       pcmpgtw         $f27, $f28, $f29
+       pextrh          $f0, $f1, $f2
+       pinsrh_0        $f3, $f4, $f5
+       pinsrh_1        $f6, $f7, $f8
+       pinsrh_2        $f9, $f10, $f11
+       pinsrh_3        $f12, $f13, $f14
+       pmaddhw         $f15, $f16, $f17
+       pmaxsh          $f18, $f19, $f20
+       pmaxub          $f21, $f22, $f23
+       pminsh          $f24, $f25, $f26
+       pminub          $f27, $f28, $f29
+       pmovmskb        $f0, $f1
+       pmulhuh         $f2, $f3, $f4
+       pmulhh          $f5, $f6, $f7
+       pmullh          $f8, $f9, $f10
+       pmuluw          $f11, $f12, $f13
+       pasubub         $f14, $f15, $f16
+       biadd           $f17, $f18
+       pshufh          $f19, $f20, $f21
+       psllh           $f22, $f23, $f24
+       psllw           $f25, $f26, $f27
+       psrah           $f28, $f29, $f30
+       psraw           $f0, $f1, $f2
+       psrlh           $f3, $f4, $f5
+       psrlw           $f6, $f7, $f8
+       psubb           $f9, $f10, $f11
+       psubh           $f12, $f13, $f14
+       psubw           $f15, $f16, $f17
+       psubd           $f18, $f19, $f20
+       psubsb          $f21, $f22, $f23
+       psubsh          $f24, $f25, $f26
+       psubusb         $f27, $f28, $f29
+       psubush         $f0, $f1, $f2
+       punpckhbh       $f3, $f4, $f5
+       punpckhhw       $f6, $f7, $f8
+       punpckhwd       $f9, $f10, $f11
+       punpcklbh       $f12, $f13, $f14
+       punpcklhw       $f15, $f16, $f17
+       punpcklwd       $f18, $f19, $f20
+
+fixed_point_insns:
+       add             $f0, $f1, $f2
+       addu            $f3, $f4, $f5
+       dadd            $f6, $f7, $f8
+       sub             $f9, $f10, $f11
+       subu            $f12, $f13, $f14
+       dsub            $f15, $f16, $f17
+       or              $f18, $f19, $f20
+       sll             $f21, $f22, $f23
+       dsll            $f24, $f25, $f26
+       xor             $f27, $f28, $f29
+       nor             $f0, $f1, $f2
+       and             $f3, $f4, $f5
+       srl             $f6, $f7, $f8
+       dsrl            $f9, $f10, $f11
+       sra             $f12, $f13, $f14
+       dsra            $f15, $f16, $f17
+       sequ            $f18, $f19
+       sltu            $f20, $f21
+       sleu            $f22, $f23
+       seq             $f24, $f25
+       slt             $f26, $f27
+       sle             $f28, $f29

diff --git a/gas/testsuite/gas/mips/loongson-2f.d b/gas/testsuite/gas/mips/loongson-2f.d
index a4e83c9cf432c6f52d8408e889a48d02d15c6734..3f4566f3c2c30b5b5b62c822ebe3a38eccefbb68 100644 (file)
--- a/gas/testsuite/gas/mips/loongson-2f.d
+++ b/gas/testsuite/gas/mips/loongson-2f.d
@@ -39,91 +39,7 @@ Disassembly of section .text:
 .*:    7222081b        nmsub.d \$f0,\$f1,\$f2
 .*:    72c520db        nmsub.ps        \$f3,\$f4,\$f5
 
-[0-9a-f]+ <simd_insns>:
-.*:    4b420802        packsshb        \$f0,\$f1,\$f2
-.*:    4b2520c2        packsswh        \$f3,\$f4,\$f5
-.*:    4b683982        packushb        \$f6,\$f7,\$f8
-.*:    4bcb5240        paddb   \$f9,\$f10,\$f11
-.*:    4b4e6b00        paddh   \$f12,\$f13,\$f14
-.*:    4b7183c0        paddw   \$f15,\$f16,\$f17
-.*:    4bf49c80        paddd   \$f18,\$f19,\$f20
-.*:    4b97b540        paddsb  \$f21,\$f22,\$f23
-.*:    4b1ace00        paddsh  \$f24,\$f25,\$f26
-.*:    4bbde6c0        paddusb \$f27,\$f28,\$f29
-.*:    4b220800        paddush \$f0,\$f1,\$f2
-.*:    4be520c2        pandn   \$f3,\$f4,\$f5
-.*:    4b283988        pavgb   \$f6,\$f7,\$f8
-.*:    4b0b5248        pavgh   \$f9,\$f10,\$f11
-.*:    4b8e6b09        pcmpeqb \$f12,\$f13,\$f14
-.*:    4b5183c9        pcmpeqh \$f15,\$f16,\$f17
-.*:    4b149c89        pcmpeqw \$f18,\$f19,\$f20
-.*:    4bb7b549        pcmpgtb \$f21,\$f22,\$f23
-.*:    4b7ace09        pcmpgth \$f24,\$f25,\$f26
-.*:    4b3de6c9        pcmpgtw \$f27,\$f28,\$f29
-.*:    4b42080e        pextrh  \$f0,\$f1,\$f2
-.*:    4b8520c3        pinsrh_0        \$f3,\$f4,\$f5
-.*:    4ba83983        pinsrh_1        \$f6,\$f7,\$f8
-.*:    4bcb5243        pinsrh_2        \$f9,\$f10,\$f11
-.*:    4bee6b03        pinsrh_3        \$f12,\$f13,\$f14
-.*:    4b7183ce        pmaddhw \$f15,\$f16,\$f17
-.*:    4b549c88        pmaxsh  \$f18,\$f19,\$f20
-.*:    4b97b548        pmaxub  \$f21,\$f22,\$f23
-.*:    4b7ace08        pminsh  \$f24,\$f25,\$f26
-.*:    4bbde6c8        pminub  \$f27,\$f28,\$f29
-.*:    4ba0080f        pmovmskb        \$f0,\$f1
-.*:    4ba4188a        pmulhuh \$f2,\$f3,\$f4
-.*:    4b67314a        pmulhh  \$f5,\$f6,\$f7
-.*:    4b4a4a0a        pmullh  \$f8,\$f9,\$f10
-.*:    4b8d62ca        pmuluw  \$f11,\$f12,\$f13
-.*:    4b307b8d        pasubub \$f14,\$f15,\$f16
-.*:    4b80944f        biadd   \$f17,\$f18
-.*:    4b15a4c2        pshufh  \$f19,\$f20,\$f21
-.*:    4b38bd8a        psllh   \$f22,\$f23,\$f24
-.*:    4b1bd64a        psllw   \$f25,\$f26,\$f27
-.*:    4b7eef0b        psrah   \$f28,\$f29,\$f30
-.*:    4b42080b        psraw   \$f0,\$f1,\$f2
-.*:    4b2520cb        psrlh   \$f3,\$f4,\$f5
-.*:    4b08398b        psrlw   \$f6,\$f7,\$f8
-.*:    4bcb5241        psubb   \$f9,\$f10,\$f11
-.*:    4b4e6b01        psubh   \$f12,\$f13,\$f14
-.*:    4b7183c1        psubw   \$f15,\$f16,\$f17
-.*:    4bf49c81        psubd   \$f18,\$f19,\$f20
-.*:    4b97b541        psubsb  \$f21,\$f22,\$f23
-.*:    4b1ace01        psubsh  \$f24,\$f25,\$f26
-.*:    4bbde6c1        psubusb \$f27,\$f28,\$f29
-.*:    4b220801        psubush \$f0,\$f1,\$f2
-.*:    4b6520c3        punpckhbh       \$f3,\$f4,\$f5
-.*:    4b283983        punpckhhw       \$f6,\$f7,\$f8
-.*:    4bab524b        punpckhwd       \$f9,\$f10,\$f11
-.*:    4b4e6b03        punpcklbh       \$f12,\$f13,\$f14
-.*:    4b1183c3        punpcklhw       \$f15,\$f16,\$f17
-.*:    4b949c8b        punpcklwd       \$f18,\$f19,\$f20
-
-[0-9a-f]+ <fixed_point_insns>:
-.*:    4b42080c        add     \$f0,\$f1,\$f2
-.*:    4b0520cc        addu    \$f3,\$f4,\$f5
-.*:    4b68398c        dadd    \$f6,\$f7,\$f8
-.*:    4b4b524d        sub     \$f9,\$f10,\$f11
-.*:    4b0e6b0d        subu    \$f12,\$f13,\$f14
-.*:    4b7183cd        dsub    \$f15,\$f16,\$f17
-.*:    4b349c8c        or      \$f18,\$f19,\$f20
-.*:    4b17b54e        sll     \$f21,\$f22,\$f23
-.*:    4b3ace0e        dsll    \$f24,\$f25,\$f26
-.*:    4b9de6c2        xor     \$f27,\$f28,\$f29
-.*:    4ba20802        nor     \$f0,\$f1,\$f2
-.*:    4bc520c2        and     \$f3,\$f4,\$f5
-.*:    4b08398f        srl     \$f6,\$f7,\$f8
-.*:    4b2b524f        dsrl    \$f9,\$f10,\$f11
-.*:    4b4e6b0f        sra     \$f12,\$f13,\$f14
-.*:    4b7183cf        dsra    \$f15,\$f16,\$f17
-.*:    4b93900c        sequ    \$f18,\$f19
-.*:    4b95a00d        sltu    \$f20,\$f21
-.*:    4b97b00e        sleu    \$f22,\$f23
-.*:    4bb9c00c        seq     \$f24,\$f25
-.*:    4bbbd00d        slt     \$f26,\$f27
-.*:    4bbde00e        sle     \$f28,\$f29
-
-000001ac <mips5_ps_insns>:
+[0-9a-f]+ <mips5_ps_insns>:
 .*:    46c01005        abs.ps  \$f0,\$f2
 .*:    46c62080        add.ps  \$f2,\$f4,\$f6
 .*:    46ca4032        c.eq.ps \$f8,\$f10

diff --git a/gas/testsuite/gas/mips/loongson-2f.s b/gas/testsuite/gas/mips/loongson-2f.s
index 2db07ee377ddde939026f71a8a714b4b718b7370..9f71e5703a6343bb50783519623a7e687f9559dd 100644 (file)
--- a/gas/testsuite/gas/mips/loongson-2f.s
+++ b/gas/testsuite/gas/mips/loongson-2f.s
@@ -34,90 +34,6 @@ fpu_insns:
        nmsub.d         $f0, $f1, $f2
        nmsub.ps        $f3, $f4, $f5
 
-simd_insns:
-       packsshb        $f0, $f1, $f2
-       packsswh        $f3, $f4, $f5
-       packushb        $f6, $f7, $f8
-       paddb           $f9, $f10, $f11
-       paddh           $f12, $f13, $f14
-       paddw           $f15, $f16, $f17
-       paddd           $f18, $f19, $f20
-       paddsb          $f21, $f22, $f23
-       paddsh          $f24, $f25, $f26
-       paddusb         $f27, $f28, $f29
-       paddush         $f0, $f1, $f2
-       pandn           $f3, $f4, $f5
-       pavgb           $f6, $f7, $f8
-       pavgh           $f9, $f10, $f11
-       pcmpeqb         $f12, $f13, $f14
-       pcmpeqh         $f15, $f16, $f17
-       pcmpeqw         $f18, $f19, $f20
-       pcmpgtb         $f21, $f22, $f23
-       pcmpgth         $f24, $f25, $f26
-       pcmpgtw         $f27, $f28, $f29
-       pextrh          $f0, $f1, $f2
-       pinsrh_0        $f3, $f4, $f5
-       pinsrh_1        $f6, $f7, $f8
-       pinsrh_2        $f9, $f10, $f11
-       pinsrh_3        $f12, $f13, $f14
-       pmaddhw         $f15, $f16, $f17
-       pmaxsh          $f18, $f19, $f20
-       pmaxub          $f21, $f22, $f23
-       pminsh          $f24, $f25, $f26
-       pminub          $f27, $f28, $f29
-       pmovmskb        $f0, $f1
-       pmulhuh         $f2, $f3, $f4
-       pmulhh          $f5, $f6, $f7
-       pmullh          $f8, $f9, $f10
-       pmuluw          $f11, $f12, $f13
-       pasubub         $f14, $f15, $f16
-       biadd           $f17, $f18
-       pshufh          $f19, $f20, $f21
-       psllh           $f22, $f23, $f24
-       psllw           $f25, $f26, $f27
-       psrah           $f28, $f29, $f30
-       psraw           $f0, $f1, $f2
-       psrlh           $f3, $f4, $f5
-       psrlw           $f6, $f7, $f8
-       psubb           $f9, $f10, $f11
-       psubh           $f12, $f13, $f14
-       psubw           $f15, $f16, $f17
-       psubd           $f18, $f19, $f20
-       psubsb          $f21, $f22, $f23
-       psubsh          $f24, $f25, $f26
-       psubusb         $f27, $f28, $f29
-       psubush         $f0, $f1, $f2
-       punpckhbh       $f3, $f4, $f5
-       punpckhhw       $f6, $f7, $f8
-       punpckhwd       $f9, $f10, $f11
-       punpcklbh       $f12, $f13, $f14
-       punpcklhw       $f15, $f16, $f17
-       punpcklwd       $f18, $f19, $f20
-
-fixed_point_insns:
-       add             $f0, $f1, $f2
-       addu            $f3, $f4, $f5
-       dadd            $f6, $f7, $f8
-       sub             $f9, $f10, $f11
-       subu            $f12, $f13, $f14
-       dsub            $f15, $f16, $f17
-       or              $f18, $f19, $f20
-       sll             $f21, $f22, $f23
-       dsll            $f24, $f25, $f26
-       xor             $f27, $f28, $f29
-       nor             $f0, $f1, $f2
-       and             $f3, $f4, $f5
-       srl             $f6, $f7, $f8
-       dsrl            $f9, $f10, $f11
-       sra             $f12, $f13, $f14
-       dsra            $f15, $f16, $f17
-       sequ            $f18, $f19
-       sltu            $f20, $f21
-       sleu            $f22, $f23
-       seq             $f24, $f25
-       slt             $f26, $f27
-       sle             $f28, $f29
-
 mips5_ps_insns:
        abs.ps          $f0, $f2
        add.ps          $f2, $f4, $f6

diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.d b/gas/testsuite/gas/mips/loongson-3a-mmi.d
new file mode 100644 (file)
index 0000000..de69d3e
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-3a-mmi.d
@@ -0,0 +1,106 @@
+#as: -march=loongson3a -mabi=o64
+#objdump: -M reg-names=numeric -dp
+#name: Loongson-3A MMI tests
+
+.*:     file format .*
+
+private flags = .*
+
+MIPS ABI Flags Version: 0
+ISA: .*
+GPR size: .*
+CPR1 size: .*
+CPR2 size: .*
+FP ABI: .*
+ISA Extension: Loongson 3A
+ASEs:
+       Loongson MMI ASE
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <simd_insns>:
+.*:    4b420802        packsshb        \$f0,\$f1,\$f2
+.*:    4b2520c2        packsswh        \$f3,\$f4,\$f5
+.*:    4b683982        packushb        \$f6,\$f7,\$f8
+.*:    4bcb5240        paddb   \$f9,\$f10,\$f11
+.*:    4b4e6b00        paddh   \$f12,\$f13,\$f14
+.*:    4b7183c0        paddw   \$f15,\$f16,\$f17
+.*:    4bf49c80        paddd   \$f18,\$f19,\$f20
+.*:    4b97b540        paddsb  \$f21,\$f22,\$f23
+.*:    4b1ace00        paddsh  \$f24,\$f25,\$f26
+.*:    4bbde6c0        paddusb \$f27,\$f28,\$f29
+.*:    4b220800        paddush \$f0,\$f1,\$f2
+.*:    4be520c2        pandn   \$f3,\$f4,\$f5
+.*:    4b283988        pavgb   \$f6,\$f7,\$f8
+.*:    4b0b5248        pavgh   \$f9,\$f10,\$f11
+.*:    4b8e6b09        pcmpeqb \$f12,\$f13,\$f14
+.*:    4b5183c9        pcmpeqh \$f15,\$f16,\$f17
+.*:    4b149c89        pcmpeqw \$f18,\$f19,\$f20
+.*:    4bb7b549        pcmpgtb \$f21,\$f22,\$f23
+.*:    4b7ace09        pcmpgth \$f24,\$f25,\$f26
+.*:    4b3de6c9        pcmpgtw \$f27,\$f28,\$f29
+.*:    4b42080e        pextrh  \$f0,\$f1,\$f2
+.*:    4b8520c3        pinsrh_0        \$f3,\$f4,\$f5
+.*:    4ba83983        pinsrh_1        \$f6,\$f7,\$f8
+.*:    4bcb5243        pinsrh_2        \$f9,\$f10,\$f11
+.*:    4bee6b03        pinsrh_3        \$f12,\$f13,\$f14
+.*:    4b7183ce        pmaddhw \$f15,\$f16,\$f17
+.*:    4b549c88        pmaxsh  \$f18,\$f19,\$f20
+.*:    4b97b548        pmaxub  \$f21,\$f22,\$f23
+.*:    4b7ace08        pminsh  \$f24,\$f25,\$f26
+.*:    4bbde6c8        pminub  \$f27,\$f28,\$f29
+.*:    4ba0080f        pmovmskb        \$f0,\$f1
+.*:    4ba4188a        pmulhuh \$f2,\$f3,\$f4
+.*:    4b67314a        pmulhh  \$f5,\$f6,\$f7
+.*:    4b4a4a0a        pmullh  \$f8,\$f9,\$f10
+.*:    4b8d62ca        pmuluw  \$f11,\$f12,\$f13
+.*:    4b307b8d        pasubub \$f14,\$f15,\$f16
+.*:    4b80944f        biadd   \$f17,\$f18
+.*:    4b15a4c2        pshufh  \$f19,\$f20,\$f21
+.*:    4b38bd8a        psllh   \$f22,\$f23,\$f24
+.*:    4b1bd64a        psllw   \$f25,\$f26,\$f27
+.*:    4b7eef0b        psrah   \$f28,\$f29,\$f30
+.*:    4b42080b        psraw   \$f0,\$f1,\$f2
+.*:    4b2520cb        psrlh   \$f3,\$f4,\$f5
+.*:    4b08398b        psrlw   \$f6,\$f7,\$f8
+.*:    4bcb5241        psubb   \$f9,\$f10,\$f11
+.*:    4b4e6b01        psubh   \$f12,\$f13,\$f14
+.*:    4b7183c1        psubw   \$f15,\$f16,\$f17
+.*:    4bf49c81        psubd   \$f18,\$f19,\$f20
+.*:    4b97b541        psubsb  \$f21,\$f22,\$f23
+.*:    4b1ace01        psubsh  \$f24,\$f25,\$f26
+.*:    4bbde6c1        psubusb \$f27,\$f28,\$f29
+.*:    4b220801        psubush \$f0,\$f1,\$f2
+.*:    4b6520c3        punpckhbh       \$f3,\$f4,\$f5
+.*:    4b283983        punpckhhw       \$f6,\$f7,\$f8
+.*:    4bab524b        punpckhwd       \$f9,\$f10,\$f11
+.*:    4b4e6b03        punpcklbh       \$f12,\$f13,\$f14
+.*:    4b1183c3        punpcklhw       \$f15,\$f16,\$f17
+.*:    4b949c8b        punpcklwd       \$f18,\$f19,\$f20
+
+[0-9a-f]+ <fixed_point_insns>:
+.*:    4b42080c        add     \$f0,\$f1,\$f2
+.*:    4b0520cc        addu    \$f3,\$f4,\$f5
+.*:    4b68398c        dadd    \$f6,\$f7,\$f8
+.*:    4b4b524d        sub     \$f9,\$f10,\$f11
+.*:    4b0e6b0d        subu    \$f12,\$f13,\$f14
+.*:    4b7183cd        dsub    \$f15,\$f16,\$f17
+.*:    4b349c8c        or      \$f18,\$f19,\$f20
+.*:    4b17b54e        sll     \$f21,\$f22,\$f23
+.*:    4b3ace0e        dsll    \$f24,\$f25,\$f26
+.*:    4b9de6c2        xor     \$f27,\$f28,\$f29
+.*:    4ba20802        nor     \$f0,\$f1,\$f2
+.*:    4bc520c2        and     \$f3,\$f4,\$f5
+.*:    4b08398f        srl     \$f6,\$f7,\$f8
+.*:    4b2b524f        dsrl    \$f9,\$f10,\$f11
+.*:    4b4e6b0f        sra     \$f12,\$f13,\$f14
+.*:    4b7183cf        dsra    \$f15,\$f16,\$f17
+.*:    4b93900c        sequ    \$f18,\$f19
+.*:    4b95a00d        sltu    \$f20,\$f21
+.*:    4b97b00e        sleu    \$f22,\$f23
+.*:    4bb9c00c        seq     \$f24,\$f25
+.*:    4bbbd00d        slt     \$f26,\$f27
+.*:    4bbde00e        sle     \$f28,\$f29
+#pass

diff --git a/gas/testsuite/gas/mips/loongson-3a-mmi.s b/gas/testsuite/gas/mips/loongson-3a-mmi.s
new file mode 100644 (file)
index 0000000..e87d66e
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-3a-mmi.s
@@ -0,0 +1,86 @@
+       .text
+       .set noreorder
+
+simd_insns:
+       packsshb        $f0, $f1, $f2
+       packsswh        $f3, $f4, $f5
+       packushb        $f6, $f7, $f8
+       paddb           $f9, $f10, $f11
+       paddh           $f12, $f13, $f14
+       paddw           $f15, $f16, $f17
+       paddd           $f18, $f19, $f20
+       paddsb          $f21, $f22, $f23
+       paddsh          $f24, $f25, $f26
+       paddusb         $f27, $f28, $f29
+       paddush         $f0, $f1, $f2
+       pandn           $f3, $f4, $f5
+       pavgb           $f6, $f7, $f8
+       pavgh           $f9, $f10, $f11
+       pcmpeqb         $f12, $f13, $f14
+       pcmpeqh         $f15, $f16, $f17
+       pcmpeqw         $f18, $f19, $f20
+       pcmpgtb         $f21, $f22, $f23
+       pcmpgth         $f24, $f25, $f26
+       pcmpgtw         $f27, $f28, $f29
+       pextrh          $f0, $f1, $f2
+       pinsrh_0        $f3, $f4, $f5
+       pinsrh_1        $f6, $f7, $f8
+       pinsrh_2        $f9, $f10, $f11
+       pinsrh_3        $f12, $f13, $f14
+       pmaddhw         $f15, $f16, $f17
+       pmaxsh          $f18, $f19, $f20
+       pmaxub          $f21, $f22, $f23
+       pminsh          $f24, $f25, $f26
+       pminub          $f27, $f28, $f29
+       pmovmskb        $f0, $f1
+       pmulhuh         $f2, $f3, $f4
+       pmulhh          $f5, $f6, $f7
+       pmullh          $f8, $f9, $f10
+       pmuluw          $f11, $f12, $f13
+       pasubub         $f14, $f15, $f16
+       biadd           $f17, $f18
+       pshufh          $f19, $f20, $f21
+       psllh           $f22, $f23, $f24
+       psllw           $f25, $f26, $f27
+       psrah           $f28, $f29, $f30
+       psraw           $f0, $f1, $f2
+       psrlh           $f3, $f4, $f5
+       psrlw           $f6, $f7, $f8
+       psubb           $f9, $f10, $f11
+       psubh           $f12, $f13, $f14
+       psubw           $f15, $f16, $f17
+       psubd           $f18, $f19, $f20
+       psubsb          $f21, $f22, $f23
+       psubsh          $f24, $f25, $f26
+       psubusb         $f27, $f28, $f29
+       psubush         $f0, $f1, $f2
+       punpckhbh       $f3, $f4, $f5
+       punpckhhw       $f6, $f7, $f8
+       punpckhwd       $f9, $f10, $f11
+       punpcklbh       $f12, $f13, $f14
+       punpcklhw       $f15, $f16, $f17
+       punpcklwd       $f18, $f19, $f20
+
+fixed_point_insns:
+       add             $f0, $f1, $f2
+       addu            $f3, $f4, $f5
+       dadd            $f6, $f7, $f8
+       sub             $f9, $f10, $f11
+       subu            $f12, $f13, $f14
+       dsub            $f15, $f16, $f17
+       or              $f18, $f19, $f20
+       sll             $f21, $f22, $f23
+       dsll            $f24, $f25, $f26
+       xor             $f27, $f28, $f29
+       nor             $f0, $f1, $f2
+       and             $f3, $f4, $f5
+       srl             $f6, $f7, $f8
+       dsrl            $f9, $f10, $f11
+       sra             $f12, $f13, $f14
+       dsra            $f15, $f16, $f17
+       sequ            $f18, $f19
+       sltu            $f20, $f21
+       sleu            $f22, $f23
+       seq             $f24, $f25
+       slt             $f26, $f27
+       sle             $f28, $f29

diff --git a/gas/testsuite/gas/mips/loongson-3a.d b/gas/testsuite/gas/mips/loongson-3a.d
index 4839ff7290395b17fd8c7b25d91389cd9cdee9c4..108c82d4a1caec100ca408f809203be9fbeabed6 100644 (file)
--- a/gas/testsuite/gas/mips/loongson-3a.d
+++ b/gas/testsuite/gas/mips/loongson-3a.d
@@ -22,88 +22,4 @@ Disassembly of section .text:
 .*:    73dfe81e        gsmodu  \$29,\$30,\$31
 .*:    7064101d        gsdmod  \$2,\$3,\$4
 .*:    70c7281f        gsdmodu \$5,\$6,\$7
-
-[0-9a-f]+ <simd_insns>:
-.*:    4b420802        packsshb        \$f0,\$f1,\$f2
-.*:    4b2520c2        packsswh        \$f3,\$f4,\$f5
-.*:    4b683982        packushb        \$f6,\$f7,\$f8
-.*:    4bcb5240        paddb   \$f9,\$f10,\$f11
-.*:    4b4e6b00        paddh   \$f12,\$f13,\$f14
-.*:    4b7183c0        paddw   \$f15,\$f16,\$f17
-.*:    4bf49c80        paddd   \$f18,\$f19,\$f20
-.*:    4b97b540        paddsb  \$f21,\$f22,\$f23
-.*:    4b1ace00        paddsh  \$f24,\$f25,\$f26
-.*:    4bbde6c0        paddusb \$f27,\$f28,\$f29
-.*:    4b220800        paddush \$f0,\$f1,\$f2
-.*:    4be520c2        pandn   \$f3,\$f4,\$f5
-.*:    4b283988        pavgb   \$f6,\$f7,\$f8
-.*:    4b0b5248        pavgh   \$f9,\$f10,\$f11
-.*:    4b8e6b09        pcmpeqb \$f12,\$f13,\$f14
-.*:    4b5183c9        pcmpeqh \$f15,\$f16,\$f17
-.*:    4b149c89        pcmpeqw \$f18,\$f19,\$f20
-.*:    4bb7b549        pcmpgtb \$f21,\$f22,\$f23
-.*:    4b7ace09        pcmpgth \$f24,\$f25,\$f26
-.*:    4b3de6c9        pcmpgtw \$f27,\$f28,\$f29
-.*:    4b42080e        pextrh  \$f0,\$f1,\$f2
-.*:    4b8520c3        pinsrh_0        \$f3,\$f4,\$f5
-.*:    4ba83983        pinsrh_1        \$f6,\$f7,\$f8
-.*:    4bcb5243        pinsrh_2        \$f9,\$f10,\$f11
-.*:    4bee6b03        pinsrh_3        \$f12,\$f13,\$f14
-.*:    4b7183ce        pmaddhw \$f15,\$f16,\$f17
-.*:    4b549c88        pmaxsh  \$f18,\$f19,\$f20
-.*:    4b97b548        pmaxub  \$f21,\$f22,\$f23
-.*:    4b7ace08        pminsh  \$f24,\$f25,\$f26
-.*:    4bbde6c8        pminub  \$f27,\$f28,\$f29
-.*:    4ba0080f        pmovmskb        \$f0,\$f1
-.*:    4ba4188a        pmulhuh \$f2,\$f3,\$f4
-.*:    4b67314a        pmulhh  \$f5,\$f6,\$f7
-.*:    4b4a4a0a        pmullh  \$f8,\$f9,\$f10
-.*:    4b8d62ca        pmuluw  \$f11,\$f12,\$f13
-.*:    4b307b8d        pasubub \$f14,\$f15,\$f16
-.*:    4b80944f        biadd   \$f17,\$f18
-.*:    4b15a4c2        pshufh  \$f19,\$f20,\$f21
-.*:    4b38bd8a        psllh   \$f22,\$f23,\$f24
-.*:    4b1bd64a        psllw   \$f25,\$f26,\$f27
-.*:    4b7eef0b        psrah   \$f28,\$f29,\$f30
-.*:    4b42080b        psraw   \$f0,\$f1,\$f2
-.*:    4b2520cb        psrlh   \$f3,\$f4,\$f5
-.*:    4b08398b        psrlw   \$f6,\$f7,\$f8
-.*:    4bcb5241        psubb   \$f9,\$f10,\$f11
-.*:    4b4e6b01        psubh   \$f12,\$f13,\$f14
-.*:    4b7183c1        psubw   \$f15,\$f16,\$f17
-.*:    4bf49c81        psubd   \$f18,\$f19,\$f20
-.*:    4b97b541        psubsb  \$f21,\$f22,\$f23
-.*:    4b1ace01        psubsh  \$f24,\$f25,\$f26
-.*:    4bbde6c1        psubusb \$f27,\$f28,\$f29
-.*:    4b220801        psubush \$f0,\$f1,\$f2
-.*:    4b6520c3        punpckhbh       \$f3,\$f4,\$f5
-.*:    4b283983        punpckhhw       \$f6,\$f7,\$f8
-.*:    4bab524b        punpckhwd       \$f9,\$f10,\$f11
-.*:    4b4e6b03        punpcklbh       \$f12,\$f13,\$f14
-.*:    4b1183c3        punpcklhw       \$f15,\$f16,\$f17
-.*:    4b949c8b        punpcklwd       \$f18,\$f19,\$f20
-
-[0-9a-f]+ <fixed_point_insns>:
-.*:    4b42080c        add     \$f0,\$f1,\$f2
-.*:    4b0520cc        addu    \$f3,\$f4,\$f5
-.*:    4b68398c        dadd    \$f6,\$f7,\$f8
-.*:    4b4b524d        sub     \$f9,\$f10,\$f11
-.*:    4b0e6b0d        subu    \$f12,\$f13,\$f14
-.*:    4b7183cd        dsub    \$f15,\$f16,\$f17
-.*:    4b349c8c        or      \$f18,\$f19,\$f20
-.*:    4b17b54e        sll     \$f21,\$f22,\$f23
-.*:    4b3ace0e        dsll    \$f24,\$f25,\$f26
-.*:    4b9de6c2        xor     \$f27,\$f28,\$f29
-.*:    4ba20802        nor     \$f0,\$f1,\$f2
-.*:    4bc520c2        and     \$f3,\$f4,\$f5
-.*:    4b08398f        srl     \$f6,\$f7,\$f8
-.*:    4b2b524f        dsrl    \$f9,\$f10,\$f11
-.*:    4b4e6b0f        sra     \$f12,\$f13,\$f14
-.*:    4b7183cf        dsra    \$f15,\$f16,\$f17
-.*:    4b93900c        sequ    \$f18,\$f19
-.*:    4b95a00d        sltu    \$f20,\$f21
-.*:    4b97b00e        sleu    \$f22,\$f23
-.*:    4bb9c00c        seq     \$f24,\$f25
-.*:    4bbbd00d        slt     \$f26,\$f27
-.*:    4bbde00e        sle     \$f28,\$f29
 #pass

diff --git a/gas/testsuite/gas/mips/loongson-3a.s b/gas/testsuite/gas/mips/loongson-3a.s
index 0a0f71a3704376105e4dd43d41b79aa6cbf5032e..2babb4e79f6b5687e273ca30227a736527392c13 100644 (file)
--- a/gas/testsuite/gas/mips/loongson-3a.s
+++ b/gas/testsuite/gas/mips/loongson-3a.s
@@ -17,87 +17,3 @@ integer_insns:
        gsmodu          $29, $30, $31
        gsdmod          $2, $3, $4
        gsdmodu         $5, $6, $7
-
-simd_insns:
-       packsshb        $f0, $f1, $f2
-       packsswh        $f3, $f4, $f5
-       packushb        $f6, $f7, $f8
-       paddb           $f9, $f10, $f11
-       paddh           $f12, $f13, $f14
-       paddw           $f15, $f16, $f17
-       paddd           $f18, $f19, $f20
-       paddsb          $f21, $f22, $f23
-       paddsh          $f24, $f25, $f26
-       paddusb         $f27, $f28, $f29
-       paddush         $f0, $f1, $f2
-       pandn           $f3, $f4, $f5
-       pavgb           $f6, $f7, $f8
-       pavgh           $f9, $f10, $f11
-       pcmpeqb         $f12, $f13, $f14
-       pcmpeqh         $f15, $f16, $f17
-       pcmpeqw         $f18, $f19, $f20
-       pcmpgtb         $f21, $f22, $f23
-       pcmpgth         $f24, $f25, $f26
-       pcmpgtw         $f27, $f28, $f29
-       pextrh          $f0, $f1, $f2
-       pinsrh_0        $f3, $f4, $f5
-       pinsrh_1        $f6, $f7, $f8
-       pinsrh_2        $f9, $f10, $f11
-       pinsrh_3        $f12, $f13, $f14
-       pmaddhw         $f15, $f16, $f17
-       pmaxsh          $f18, $f19, $f20
-       pmaxub          $f21, $f22, $f23
-       pminsh          $f24, $f25, $f26
-       pminub          $f27, $f28, $f29
-       pmovmskb        $f0, $f1
-       pmulhuh         $f2, $f3, $f4
-       pmulhh          $f5, $f6, $f7
-       pmullh          $f8, $f9, $f10
-       pmuluw          $f11, $f12, $f13
-       pasubub         $f14, $f15, $f16
-       biadd           $f17, $f18
-       pshufh          $f19, $f20, $f21
-       psllh           $f22, $f23, $f24
-       psllw           $f25, $f26, $f27
-       psrah           $f28, $f29, $f30
-       psraw           $f0, $f1, $f2
-       psrlh           $f3, $f4, $f5
-       psrlw           $f6, $f7, $f8
-       psubb           $f9, $f10, $f11
-       psubh           $f12, $f13, $f14
-       psubw           $f15, $f16, $f17
-       psubd           $f18, $f19, $f20
-       psubsb          $f21, $f22, $f23
-       psubsh          $f24, $f25, $f26
-       psubusb         $f27, $f28, $f29
-       psubush         $f0, $f1, $f2
-       punpckhbh       $f3, $f4, $f5
-       punpckhhw       $f6, $f7, $f8
-       punpckhwd       $f9, $f10, $f11
-       punpcklbh       $f12, $f13, $f14
-       punpcklhw       $f15, $f16, $f17
-       punpcklwd       $f18, $f19, $f20
-
-fixed_point_insns:
-       add             $f0, $f1, $f2
-       addu            $f3, $f4, $f5
-       dadd            $f6, $f7, $f8
-       sub             $f9, $f10, $f11
-       subu            $f12, $f13, $f14
-       dsub            $f15, $f16, $f17
-       or              $f18, $f19, $f20
-       sll             $f21, $f22, $f23
-       dsll            $f24, $f25, $f26
-       xor             $f27, $f28, $f29
-       nor             $f0, $f1, $f2
-       and             $f3, $f4, $f5
-       srl             $f6, $f7, $f8
-       dsrl            $f9, $f10, $f11
-       sra             $f12, $f13, $f14
-       dsra            $f15, $f16, $f17
-       sequ            $f18, $f19
-       sltu            $f20, $f21
-       sleu            $f22, $f23
-       seq             $f24, $f25
-       slt             $f26, $f27
-       sle             $f28, $f29

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 78969ff174a96f26bc777f336c47046858ba06dd..ad371e13b54321047c7ece76bcf0855ba0592039 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1391,6 +1391,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "loongson-3a-2"
     run_dump_test "loongson-3a-3"
 
+    run_dump_test "loongson-2f-mmi"
+    run_dump_test "loongson-3a-mmi"
+
     if { $has_newabi } {
        run_dump_test_arches "octeon"   [mips_arch_list_matching octeon]
     }

diff --git a/include/ChangeLog b/include/ChangeLog
index a3b1af88e334033034e7fc824afda4c114f4404b..64224c6e00bc59899aff86b743c83e5751ca85e4 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+           Maciej W. Rozycki  <macro@mips.com>
+
+       * elf/mips.h (AFL_ASE_MMI): New macro.
+       (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
+       * opcode/mips.h (ASE_LOONGSON_MMI): New macro.
+
 2018-07-17  Maciej W. Rozycki  <macro@mips.com>
 
        * bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.

diff --git a/include/elf/mips.h b/include/elf/mips.h
index 4e2cde3279ddbda2cf4702084e43632da9b0c062..2d73212b27cfa7f701099fc67c8fe26b96673185 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1238,7 +1238,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
 #define AFL_ASE_CRC          0x00008000 /* CRC ASE.  */
 #define AFL_ASE_RESERVED1    0x00010000 /* Reserved by MIPS Tech for WIP.  */
 #define AFL_ASE_GINV         0x00020000 /* GINV ASE.  */
-#define AFL_ASE_MASK         0x0002ffff /* All ASEs.  */
+#define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE.  */
+#define AFL_ASE_MASK         0x0004ffff /* All ASEs.  */
 
 /* Values for the isa_ext word of an ABI flags structure.  */
 

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 1ab1780567e7b8b3d7ccb75632b9cdd8a0b32b45..05614c164837c2488152a300f99166c586e284e3 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1302,6 +1302,8 @@ static const unsigned int mips_isa_table[] = {
 #define ASE_CRC64              0x00080000
 /* Global INValidate Extension.  */
 #define ASE_GINV               0x00100000
+/* Loongson MultiMedia extensions Instructions (MMI).  */
+#define ASE_LOONGSON_MMI       0x00200000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5e71f756803ce6c8652c8d31730cfd0b2b797fa4..076af1f5025ff4db69af5786930a6accaade9c2f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+           Maciej W. Rozycki  <macro@mips.com>
+
+       * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
+       loongson3a descriptors.
+       (parse_mips_ase_option): Handle -M loongson-mmi option.
+       (print_mips_disassembler_options): Document -M loongson-mmi.
+       * mips-opc.c (LMMI): New macro.
+       (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
+       instructions.
+
 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index bbf21328e86ddf3d0e1a552c8d159b7f7e5a34c5..466301637f9cbba680fe541c55152241a3f4fdbc 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -626,11 +626,11 @@ const struct mips_arch_choice mips_arch_choices[] =
     NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
-    ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
+    ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
     NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
-    ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
+    ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
     NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
 
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
@@ -935,6 +935,12 @@ parse_mips_ase_option (const char *option)
       return TRUE;
     }
 
+  if (CONST_STRNEQ (option, "loongson-mmi"))
+    {
+      mips_ase |= ASE_LOONGSON_MMI;
+      return TRUE;
+    }
+
   return FALSE;
 }
 
@@ -2582,6 +2588,10 @@ static struct
   { "ginv",       N_("Recognize the Global INValidate (GINV) ASE "
                     "instructions.\n"),
                  MIPS_OPTION_ARG_NONE },
+  { "loongson-mmi",
+                 N_("Recognize the Loongson MultiMedia extensions "
+                    "Instructions (MMI) ASE instructions.\n"),
+                 MIPS_OPTION_ARG_NONE },
   { "gpr-names=", N_("Print GPR names according to specified ABI.\n\
                   Default: based on binary being disassembled.\n"),
                  MIPS_OPTION_ARG_ABI },

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 1cbcbc6abccd09e49fb175767e6a31324598e891..31532f88a8dd7f3229a2af97facc363cb09ca4e4 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -412,6 +412,9 @@ decode_mips_operand (const char *p)
 /* Global INValidate (GINV) support.  */
 #define GINV   ASE_GINV
 
+/* Loongson MultiMedia extensions Instructions (MMI) support.  */
+#define LMMI   ASE_LOONGSON_MMI
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -652,7 +655,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add",                        "d,v,t",        0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"add",                        "D,S,T",        0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"add.s",              "D,V,T",        0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"add.d",              "D,V,T",        0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"add.ob",             "X,Y,Q",        0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -673,7 +676,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu",               "d,v,t",        0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"addu",               "t,r,I",        0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"addu",               "D,S,T",        0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"addu",               "D,S,T",        0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"addu",               "D,S,T",        0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"alni.ob",            "X,Y,Z,O",      0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"alni.ob",            "D,S,T,%",      0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"alni.qh",            "X,Y,Z,O",      0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -683,7 +686,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and",                        "d,v,t",        0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"and",                        "t,r,I",        0,    (int) M_AND_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"and",                        "D,S,T",        0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"and",                        "D,S,T",        0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"and",                        "D,S,T",        0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"and.ob",             "X,Y,Q",        0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"and.ob",             "D,S,Q",        0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"and.qh",             "X,Y,Q",        0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1001,7 +1004,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dadd",               "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"dadd",               "D,S,T",        0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"daddi",              "t,r,j",        0x60000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      I69 },
 {"daddiu",             "t,r,j",        0x64000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      0 },
 {"daddu",              "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
@@ -1141,25 +1144,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",               "d,w,>",        0x0000003c, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsll32 */
 {"dsll",               "d,w,<",        0x00000038, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsll",               "D,S,T",        0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsll",               "D,S,T",        0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsll",               "D,S,T",        0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsrav",              "d,t,s",        0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsra32",             "d,w,<",        0x0000003f, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsra",               "d,w,s",        0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 }, /* dsrav */
 {"dsra",               "d,w,>",        0x0000003f, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsra32 */
 {"dsra",               "d,w,<",        0x0000003b, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsra",               "D,S,T",        0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsra",               "D,S,T",        0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsra",               "D,S,T",        0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsrlv",              "d,t,s",        0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsrl32",             "d,w,<",        0x0000003e, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsrl",               "d,w,s",        0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 }, /* dsrlv */
 {"dsrl",               "d,w,>",        0x0000003e, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsrl32 */
 {"dsrl",               "d,w,<",        0x0000003a, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsrl",               "D,S,T",        0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsub",               "d,v,t",        0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"dsub",               "D,S,T",        0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsubu",              "d,v,t",        0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsubu",              "d,v,I",        0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"dvpe",               "",             0x41600001, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
@@ -1628,7 +1631,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",                        "d,v,t",        0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"nor",                        "t,r,I",        0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"nor",                        "D,S,T",        0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"nor",                        "D,S,T",        0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"nor",                        "D,S,T",        0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"nor.ob",             "X,Y,Q",        0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"nor.ob",             "D,S,Q",        0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"nor.qh",             "X,Y,Q",        0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1636,7 +1639,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"or",                 "d,v,t",        0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"or",                 "t,r,I",        0,    (int) M_OR_I,     INSN_MACRO,             0,              I1,             0,      0 },
 {"or",                 "D,S,T",        0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"or",                 "D,S,T",        0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"or",                 "D,S,T",        0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"or.ob",              "X,Y,Q",        0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"or.ob",              "D,S,Q",        0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"or.qh",              "X,Y,Q",        0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1849,7 +1852,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"seq",                        "d,v,t",        0,    (int) M_SEQ,      INSN_MACRO,             0,              I1,             0,      0 },
 {"seq",                        "d,v,I",        0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"seq",                        "S,T",          0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"seq",                        "S,T",          0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"seq",                        "S,T",          0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"seqi",               "t,r,+Q",       0x7000002e, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"sge",                        "d,v,t",        0,    (int) M_SGE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sge",                        "d,v,I",        0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1879,29 +1882,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sle",                        "d,v,t",        0,    (int) M_SLE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "d,v,I",        0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "S,T",          0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sle",                        "S,T",          0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sle",                        "S,T",          0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sleu",               "d,v,t",        0,    (int) M_SLEU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"sleu",               "d,v,I",        0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"sleu",               "S,T",          0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sleu",               "S,T",          0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sleu",               "S,T",          0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sllv",               "d,t,s",        0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sll",                        "d,w,s",        0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* sllv */
 {"sll",                        "d,w,<",        0x00000000, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sll",                        "D,S,T",        0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"sll",                        "D,S,T",        0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"sll",                        "D,S,T",        0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sll.ob",             "X,Y,Q",        0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"sll.ob",             "D,S,Q",        0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"sll.qh",             "X,Y,Q",        0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"slt",                        "d,v,t",        0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"slt",                        "d,v,I",        0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"slt",                        "S,T",          0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"slt",                        "S,T",          0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"slt",                        "S,T",          0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"slti",               "t,r,j",        0x28000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sltiu",              "t,r,j",        0x2c000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sltu",               "d,v,t",        0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sltu",               "d,v,I",        0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"sltu",               "S,T",          0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sltu",               "S,T",          0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sltu",               "S,T",          0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sne",                        "d,v,t",        0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
 {"sne",                        "d,v,t",        0,    (int) M_SNE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sne",                        "d,v,I",        0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1917,13 +1920,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sra",                        "d,w,s",        0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* srav */
 {"sra",                        "d,w,<",        0x00000003, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sra",                        "D,S,T",        0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"sra",                        "D,S,T",        0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"sra",                        "D,S,T",        0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sra.qh",             "X,Y,Q",        0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"srlv",               "d,t,s",        0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"srl",                        "d,w,s",        0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* srlv */
 {"srl",                        "d,w,<",        0x00000002, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"srl",                        "D,S,T",        0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"srl",                        "D,S,T",        0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"srl",                        "D,S,T",        0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"srl.ob",             "X,Y,Q",        0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"srl.ob",             "D,S,Q",        0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"srl.qh",             "X,Y,Q",        0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1932,7 +1935,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sub",                        "d,v,t",        0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"sub",                        "D,S,T",        0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"sub.d",              "D,V,T",        0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"sub.s",              "D,V,T",        0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"sub.ob",             "X,Y,Q",        0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -1948,7 +1951,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",               "d,v,t",        0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"subu",               "d,v,I",        0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"subu",               "D,S,T",        0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"suspend",            "",             0x42000022, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      I37},
 {"sw",                 "t,o(b)",       0xac000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
@@ -2069,7 +2072,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",                        "d,v,t",        0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"xor",                        "t,r,I",        0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"xor",                        "D,S,T",        0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"xor",                        "D,S,T",        0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"xor",                        "D,S,T",        0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"xor.ob",             "X,Y,Q",        0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"xor.ob",             "D,S,Q",        0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"xor.qh",             "X,Y,Q",        0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -2470,139 +2473,139 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmodu.g",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
 {"gsdmodu",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
 {"packsshb",           "D,S,T",        0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packsswh",           "D,S,T",        0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packsswh",           "D,S,T",        0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packsswh",           "D,S,T",        0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packushb",           "D,S,T",        0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packushb",           "D,S,T",        0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packushb",           "D,S,T",        0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddb",              "D,S,T",        0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddb",              "D,S,T",        0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddb",              "D,S,T",        0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddb",              "d,s,t",        0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddh",              "D,S,T",        0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"paddh",              "d,s,t",        0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
-{"paddh",              "D,S,T",        0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddh",              "D,S,T",        0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddw",              "D,S,T",        0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddw",              "D,S,T",        0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddw",              "D,S,T",        0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddw",              "d,s,t",        0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddd",              "D,S,T",        0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddd",              "D,S,T",        0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddd",              "D,S,T",        0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsb",             "D,S,T",        0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddsb",             "D,S,T",        0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddsb",             "D,S,T",        0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsb",             "d,s,t",        0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddsh",             "D,S,T",        0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddsh",             "D,S,T",        0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddsh",             "D,S,T",        0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsh",             "d,s,t",        0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddusb",            "D,S,T",        0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddusb",            "D,S,T",        0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddusb",            "D,S,T",        0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddush",            "D,S,T",        0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddush",            "D,S,T",        0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddush",            "D,S,T",        0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pandn",              "D,S,T",        0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pandn",              "D,S,T",        0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pandn",              "D,S,T",        0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pavgb",              "D,S,T",        0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pavgb",              "D,S,T",        0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pavgb",              "D,S,T",        0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pavgh",              "D,S,T",        0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pavgh",              "D,S,T",        0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pavgh",              "D,S,T",        0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqb",            "D,S,T",        0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqb",            "D,S,T",        0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqb",            "D,S,T",        0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqh",            "D,S,T",        0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqh",            "D,S,T",        0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqh",            "D,S,T",        0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqw",            "D,S,T",        0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqw",            "D,S,T",        0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqw",            "D,S,T",        0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgtb",            "D,S,T",        0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgtb",            "D,S,T",        0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgtb",            "D,S,T",        0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgth",            "D,S,T",        0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgth",            "D,S,T",        0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgth",            "D,S,T",        0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgtw",            "D,S,T",        0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgtw",            "D,S,T",        0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgtw",            "D,S,T",        0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pextrh",             "D,S,T",        0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pextrh",             "D,S,T",        0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pextrh",             "D,S,T",        0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_0",           "D,S,T",        0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_0",           "D,S,T",        0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_0",           "D,S,T",        0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_1",           "D,S,T",        0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_1",           "D,S,T",        0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_1",           "D,S,T",        0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_2",           "D,S,T",        0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_2",           "D,S,T",        0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_2",           "D,S,T",        0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_3",           "D,S,T",        0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_3",           "D,S,T",        0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_3",           "D,S,T",        0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaddhw",            "D,S,T",        0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaddhw",            "D,S,T",        0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaddhw",            "D,S,T",        0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaxsh",             "D,S,T",        0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaxsh",             "D,S,T",        0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaxsh",             "D,S,T",        0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaxub",             "D,S,T",        0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaxub",             "D,S,T",        0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaxub",             "D,S,T",        0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pminsh",             "D,S,T",        0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pminsh",             "D,S,T",        0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pminsh",             "D,S,T",        0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pminub",             "D,S,T",        0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pminub",             "D,S,T",        0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pminub",             "D,S,T",        0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmovmskb",           "D,S",          0x46a00005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"pmovmskb",           "D,S",          0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2F|IL3A,      0,      0 },
+{"pmovmskb",           "D,S",          0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              0,              LMMI,   0 },
 {"pmulhuh",            "D,S,T",        0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmulhuh",            "D,S,T",        0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmulhuh",            "D,S,T",        0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmulhh",             "D,S,T",        0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmulhh",             "D,S,T",        0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmulhh",             "D,S,T",        0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmullh",             "D,S,T",        0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmullh",             "D,S,T",        0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmullh",             "D,S,T",        0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmuluw",             "D,S,T",        0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmuluw",             "D,S,T",        0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmuluw",             "D,S,T",        0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pasubub",            "D,S,T",        0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pasubub",            "D,S,T",        0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pasubub",            "D,S,T",        0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"biadd",              "D,S",          0x46800005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"biadd",              "D,S",          0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2F|IL3A,      0,      0 },
+{"biadd",              "D,S",          0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              0,              LMMI,   0 },
 {"pshufh",             "D,S,T",        0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pshufh",             "D,S,T",        0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pshufh",             "D,S,T",        0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllh",              "D,S,T",        0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psllh",              "D,S,T",        0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psllh",              "D,S,T",        0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllh",              "d,t,<",        0x70000034, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psllw",              "D,S,T",        0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psllw",              "D,S,T",        0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psllw",              "D,S,T",        0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllw",              "d,t,<",        0x7000003c, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrah",              "D,S,T",        0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrah",              "D,S,T",        0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrah",              "D,S,T",        0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrah",              "d,t,<",        0x70000037, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psraw",              "D,S,T",        0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psraw",              "D,S,T",        0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psraw",              "D,S,T",        0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psraw",              "d,t,<",        0x7000003f, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrlh",              "D,S,T",        0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrlh",              "D,S,T",        0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrlh",              "D,S,T",        0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrlh",              "d,t,<",        0x70000036, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrlw",              "D,S,T",        0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrlw",              "D,S,T",        0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrlw",              "D,S,T",        0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrlw",              "d,t,<",        0x7000003e, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psubb",              "D,S,T",        0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubb",              "D,S,T",        0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubb",              "D,S,T",        0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubb",              "d,s,t",        0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubh",              "D,S,T",        0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubh",              "D,S,T",        0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubh",              "D,S,T",        0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubh",              "d,s,t",        0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubw",              "D,S,T",        0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubw",              "D,S,T",        0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubw",              "D,S,T",        0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubw",              "d,s,t",        0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubd",              "D,S,T",        0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubd",              "D,S,T",        0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubd",              "D,S,T",        0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsb",             "D,S,T",        0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubsb",             "D,S,T",        0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubsb",             "D,S,T",        0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsb",             "d,s,t",        0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubsh",             "D,S,T",        0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubsh",             "D,S,T",        0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubsh",             "D,S,T",        0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsh",             "d,s,t",        0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubusb",            "D,S,T",        0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubusb",            "D,S,T",        0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubusb",            "D,S,T",        0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubush",            "D,S,T",        0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubush",            "D,S,T",        0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubush",            "D,S,T",        0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhbh",          "D,S,T",        0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhbh",          "D,S,T",        0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhbh",          "D,S,T",        0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhhw",          "D,S,T",        0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhhw",          "D,S,T",        0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhhw",          "D,S,T",        0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhwd",          "D,S,T",        0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhwd",          "D,S,T",        0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhwd",          "D,S,T",        0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklbh",          "D,S,T",        0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklbh",          "D,S,T",        0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklbh",          "D,S,T",        0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklhw",          "D,S,T",        0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklhw",          "D,S,T",        0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklhw",          "D,S,T",        0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklwd",          "D,S,T",        0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklwd",          "D,S,T",        0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklwd",          "D,S,T",        0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sequ",               "S,T",          0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 /* MIPS Enhanced VA Scheme */
 {"lbue",               "t,+j(b)",      0x7c000028, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lbue",               "t,A(b)",       0,    (int) M_LBUE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },