(no commit message)

diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn
index a78a64d47b994ffba077b3381393df2c64c49922..9af15e6f2a380dd1c64a79f80b79d287ecb80857 100644 (file)
--- a/simple_v_extension/specification/bitmanip.mdwn
+++ b/simple_v_extension/specification/bitmanip.mdwn
@@ -221,24 +221,28 @@ Pseudo-code:
     def sof(rd, rs1, rs2):
         rd = 0
         setting_mode = rs2 == x0 or (regs[rs2] & 1)
+
         while i < XLEN:
             bit = 1<<i
-            if setting_mode:
-                if regs[rs1] & bit: # found a bit in rs1:
-                    # set bit, exit setting mode immediately
-                    regs[rd] |= bit
-                    setting_mode = False
-                    # Now skip any more 1s
-                    i += 1
-                    while i < XLEN:
-                        bit = 1<<i
-                        # stop at 1st zero
-                        if regs[rs1] & bit == 0:
-                            break
-                        i += 1
-            else if rs2 != x0:
-                # only reenable when predicate in use, and bit valid
+
+            # only reenable when predicate in use, and bit valid    
+            if !setting_mode && rs2 != x0:
                 if (regs[rs2] & bit):
-                    setting_mode = True # back into "setting" mode
+                    # back into "setting" mode
+                    setting_mode = True
+
+            # skipping mode
+            if !setting_mode:
+                # skip any more 1s
+                if regs[rs1] & bit == 1:
+                    i += 1
+                    continue
+
+            # setting mode, search for 1
+            if regs[rs1] & bit: # found a bit in rs1:
+                # set bit, exit setting mode immediately
+                regs[rd] |= bit
+                setting_mode = False
+
             i += 1