ARM: Add support for initparam m5 op

diff --git a/configs/common/Options.py b/configs/common/Options.py
index d5ea85090e32bd5b89a0810297d01e017b6a747a..2d4f52bc1cbb359c0e037e960481968b662832ff 100644 (file)
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -63,7 +63,8 @@ parser.add_option("--work-end-exit-count", action="store", type="int",
                   help="exit at specified work end count")
 parser.add_option("--work-begin-exit-count", action="store", type="int",
                   help="exit at specified work begin count")
-
+parser.add_option("--init-param", action="store", type="int", default=0,
+                  help="Parameter available in simulation with m5 initparam")
 
 # Checkpointing options
 ###Note that performing checkpointing via python script files will override

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 5945e5d9b6398a2f83785da572308808b784e3f4..8ae8d8310156ec387afa53f7fb34d314af4a9a24 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -151,6 +151,8 @@ if options.kernel is not None:
 if options.script is not None:
     test_sys.readfile = options.script
 
+test_sys.init_param = options.init_param
+
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 
 CacheConfig.config_cache(options, test_sys)
@@ -199,6 +201,7 @@ if len(bm) == 2:
     if options.kernel is not None:
         drive_sys.kernel = binary(options.kernel)
 
+    drive_sys.init_param = options.init_param
     root = makeDualRoot(test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1:
     root = Root(system=test_sys)

diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index 3b837cba9837c58808c90db7f7b691e498fb0095..f20908d4f835b18d11c4bff515a761f808ee071e 100644 (file)
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -191,16 +191,18 @@ let {{
 
     initparamCode = '''
 #if FULL_SYSTEM
-    Rt = PseudoInst::initParam(xc->tcBase());
+    uint64_t ip_val  = PseudoInst::initParam(xc->tcBase());
+    R0 = bits(ip_val, 31, 0);
+    R1 = bits(ip_val, 63, 32);
 #else
     PseudoInst::panicFsOnlyPseudoInst("initparam");
-    Rt = 0;
 #endif
     '''
 
     initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
                            { "code": initparamCode,
-                             "predicate_test": predicateTest })
+                             "predicate_test": predicateTest },
+                             ["IsNonSpeculative"])
     header_output += BasicDeclare.subst(initparamIop)
     decoder_output += BasicConstructor.subst(initparamIop)
     exec_output += PredOpExecute.subst(initparamIop)

diff --git a/util/m5/m5.c b/util/m5/m5.c
index fc4f5dcae5030b0661ee20d6b7c6fbebeefbc379..40328bc388338ccfd9a9313b2f8e0f4cf604a3ee 100644 (file)
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -160,8 +172,8 @@ do_initparam(int argc, char *argv[])
     if (argc != 0)
         usage();
 
- 
-    printf("%ld", m5_initparam());
+    uint64_t val = m5_initparam();
+    printf("%"PRIu64, val);
 }
 
 void