Update code so that the O3 CPU can handle not initially having anything hooked up...

src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.

--HG--
extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index da7ce00f5743520a69e5e2b20cd04e3b6fbe7526..811f4d2bc400d8451808d4c96db0ff95d3b07a1a 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -86,6 +86,8 @@ class DefaultFetch
 
         bool snoopRangeSent;
 
+        virtual void setPeer(Port *port);
+
       protected:
         /** Atomic version of receive.  Panics. */
         virtual Tick recvAtomic(PacketPtr pkt);
@@ -184,6 +186,9 @@ class DefaultFetch
     /** Initialize stage. */
     void initStage();
 
+    /** Tells the fetch stage that the Icache is set. */
+    void setIcache();
+
     /** Processes cache completion event. */
     void processCacheCompletion(PacketPtr pkt);
 

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 663cd3142e4cc9ac0e8802ace6db00e5dd039d39..34b06420dd30d0ca2cdc5cfa30fa6b3fe5f2094c 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -50,6 +50,15 @@
 
 #include <algorithm>
 
+template<class Impl>
+void
+DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
+{
+    Port::setPeer(port);
+
+    fetch->setIcache();
+}
+
 template<class Impl>
 Tick
 DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
@@ -323,12 +332,6 @@ DefaultFetch<Impl>::initStage()
         nextNPC[tid] = cpu->readNextNPC(tid);
     }
 
-    // Size of cache block.
-    cacheBlkSize = icachePort->peerBlockSize();
-
-    // Create mask to get rid of offset bits.
-    cacheBlkMask = (cacheBlkSize - 1);
-
     for (int tid=0; tid < numThreads; tid++) {
 
         fetchStatus[tid] = Running;
@@ -337,11 +340,6 @@ DefaultFetch<Impl>::initStage()
 
         memReq[tid] = NULL;
 
-        // Create space to store a cache line.
-        cacheData[tid] = new uint8_t[cacheBlkSize];
-        cacheDataPC[tid] = 0;
-        cacheDataValid[tid] = false;
-
         stalls[tid].decode = false;
         stalls[tid].rename = false;
         stalls[tid].iew = false;
@@ -349,6 +347,24 @@ DefaultFetch<Impl>::initStage()
     }
 }
 
+template<class Impl>
+void
+DefaultFetch<Impl>::setIcache()
+{
+    // Size of cache block.
+    cacheBlkSize = icachePort->peerBlockSize();
+
+    // Create mask to get rid of offset bits.
+    cacheBlkMask = (cacheBlkSize - 1);
+
+    for (int tid=0; tid < numThreads; tid++) {
+        // Create space to store a cache line.
+        cacheData[tid] = new uint8_t[cacheBlkSize];
+        cacheDataPC[tid] = 0;
+        cacheDataValid[tid] = false;
+    }
+}
+
 template<class Impl>
 void
 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)