targets: use mem_region.origin instead of mem_map definition (prepare for automatic...

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 4e46344920595ff366b397f491141d029f8dcc9b..8bbfa3cd26f2ccc88420a6ea9dd35a9c4658e45e 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -94,8 +94,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 30478c0101f85e1458495a34c8c4d9a4ad585717..55cc272acbca25e058f6f285636b7d09f349cc63 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -87,8 +87,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 041c4b4619aefd79298dcecccc5a72fffe7250cf..70b2f9fb08d51b1d7dfb81b5a89b3fbb9d7f3620 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -88,8 +88,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index a6241173b2aa4f988583acbc4c2f74994f45a4fb..36601746a7b576a95a1135a86d434fb5d3d5b661 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -123,8 +123,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 44a64d05cd96044200f917ba345835afeaea7d6d..40e20071efa7c411b5d311d58d60c639bd5a8c02 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -90,8 +90,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 8940ac4a737612eff2aaf6be4182fdbea5ef44bd..fa78b9d5d951f4667e4fb775025106546456bd9b 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 9773f9ac31efe44f4274c8b720cbde3bb3dbd9be..4d261d3c97b180dd9457822e9619afd8073135fa 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index fa74077d2677409e2fe7adb0c811fcac6f706b00..904959ed08d8f2742e3e634a3369dab41f957a37 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -48,8 +48,8 @@ class EthernetSoC(BaseSoC):
         # mac
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
 

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 412f1544e5b32dbb23fc4e96be0e350f431219ef..9951b798d4dc6380e6aafe3bbe2468ec2c205d92 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -114,8 +114,8 @@ class EthernetSoC(BaseSoC):
         # mac
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
             interface="wishbone", endianness=self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
         self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+        self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # timing constraints

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index ecf3edf6304558e122e8da493bbc943f663d28b9..36e13b1dbada35551ef32022b9b084bce956dbf1 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -158,8 +158,8 @@ class SimSoC(SoCSDRAM):
             if with_etherbone:
                 ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx":  "ethphy_eth_rx"})(ethmac)
             self.submodules.ethmac = ethmac
-            self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
             self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
+            self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
             self.add_csr("ethmac")
             self.add_interrupt("ethmac")