cpu: Disable O3CPU value forwarding with write strobes

https://gem5-review.googlesource.com/c/public/gem5/+/19173 did the same
for MinorCPU

Change-Id: I22d631a3d2032570f6e84b0f5eb018d1f84414ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23952
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 7c3e0e026c5ec5c243b22fc7e85c8646490290ba..e15d01b26c6ae1ee93accc793c029e727df9b0ef 100644 (file)
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -725,7 +725,10 @@ LSQUnit<Impl>::read(LSQRequest *req, int load_idx)
                 store_has_lower_limit && store_has_upper_limit &&
                 !req->mainRequest()->isLLSC()) {
 
-                coverage = AddrRangeCoverage::FullAddrRangeCoverage;
+                const auto& store_req = store_it->request()->mainRequest();
+                coverage = store_req->isMasked() ?
+                    AddrRangeCoverage::PartialAddrRangeCoverage :
+                    AddrRangeCoverage::FullAddrRangeCoverage;
             } else if (
                 // This is the partial store-load forwarding case where a store
                 // has only part of the load's data and the load isn't LLSC