gcc: Add extra parens to quell warnings.

Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.

diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh
index 4c4f282f1bfdd90ce64f5f555a3e2b50ec117f74..1915d822b19d0baf14793d52d16b560862c6b382 100644 (file)
--- a/src/arch/alpha/ev5.hh
+++ b/src/arch/alpha/ev5.hh
@@ -80,7 +80,7 @@ Phys2K0Seg(Addr addr)
 
 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
 inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
@@ -90,7 +90,7 @@ inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
 
 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
 inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }

diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 4f7beb19b2ee2eeef7b248af23fb89695b884543..6cf11be56143b1b0f7c814c5a79b07ec7293dd0b 100644 (file)
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -57,9 +57,9 @@ struct VAddr
     Addr level3() const
     { return PteAddr(addr >> PageShift); }
     Addr level2() const
-    { return PteAddr(addr >> NPtePageShift + PageShift); }
+    { return PteAddr(addr >> (NPtePageShift + PageShift)); }
     Addr level1() const
-    { return PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+    { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
 };
 
 struct PageTableEntry

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 84f7cc487ce9d34189d29b1d74933c152013e8bc..76c6c57261175c22025e3685657298864fade183 100644 (file)
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -53,14 +53,14 @@ inline bool
 isCallerSaveIntegerRegister(unsigned int reg)
 {
     panic("register classification not implemented");
-    return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
+    return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
 }
 
 inline bool
 isCalleeSaveIntegerRegister(unsigned int reg)
 {
     panic("register classification not implemented");
-    return (reg >= 9 && reg <= 15);
+    return reg >= 9 && reg <= 15;
 }
 
 inline bool

diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index fc3ae65d6fa57f6240857db2aa8a4e6c83abcead..6e4f7afeadf2aefa838da5168984a38e04296ab6 100755 (executable)
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -923,10 +923,10 @@ MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
 
     for (int i = 0; i<2; i++) {
         r_values[i] =
-            dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+            dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
                         SIMD_FMT_QB, UNSIGNED, &ouflag);
         r_values[i + 2] =
-            dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+            dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
                         SIMD_FMT_QB, UNSIGNED, &ouflag);
     }
 

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index b1cd03ca19a9e2da8f8e723b77fe6ed0a3df783d..0a12c4f6e8b7bd23d840192400119abbc9c2f166 100644 (file)
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -416,16 +416,16 @@ decode OPCODE_HI default Unknown::unknown() {
                                                                                Ctrl_Base_DepTag);
                                                  break;
                                                case 25:
-                                                 data = 0 | fcsr_val & 0xFE000000 >> 24
-                                                          | fcsr_val & 0x00800000 >> 23;
+                                                 data = (fcsr_val & 0xFE000000 >> 24)
+                                                     | (fcsr_val & 0x00800000 >> 23);
                                                  break;
                                                case 26:
-                                                 data = 0 | fcsr_val & 0x0003F07C;
+                                                 data = fcsr_val & 0x0003F07C;
                                                  break;
                                                case 28:
-                                                 data = 0 | fcsr_val & 0x00000F80
-                                                          | fcsr_val & 0x01000000 >> 21
-                                                          | fcsr_val & 0x00000003;
+                                                 data = (fcsr_val & 0x00000F80)
+                                                     | (fcsr_val & 0x01000000 >> 21)
+                                                     | (fcsr_val & 0x00000003);
                                                  break;
                                                case 31:
                                                  data = fcsr_val;
@@ -1963,7 +1963,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x0: decode OP_LO {
                         format IntOp {
                             0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
-                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
+                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }});
                         }
                     }
                     0x2: decode OP_LO {
@@ -2050,11 +2050,11 @@ decode OPCODE_HI default Unknown::unknown() {
         format LoadUnalignedMemory {
             0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
                         Rt.uw = mem_word << mem_shift |
-                        Rt.uw & mask(mem_shift);
+                            (Rt.uw & mask(mem_shift));
                      }});
             0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
-                        Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
-                        mem_word >> mem_shift;
+                        Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) |
+                            (mem_word >> mem_shift);
                      }});
       }
     }
@@ -2069,12 +2069,12 @@ decode OPCODE_HI default Unknown::unknown() {
         format StoreUnalignedMemory {
             0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
                         uint32_t mem_shift = 32 - reg_shift;
-                        mem_word = mem_word & (mask(reg_shift) << mem_shift) |
-                                   Rt.uw >> reg_shift;
+                        mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
+                            (Rt.uw >> reg_shift);
                      }});
             0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
                         mem_word = Rt.uw << reg_shift |
-                                   mem_word & (mask(reg_shift));
+                            (mem_word & (mask(reg_shift)));
                      }});
         }
         format CP0Control {

diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index 8c43a7b0c6ba7377e0b149eb010fbd71df53fcc3..bbed94194641db02bf67f1ba872cf910763dfd50 100755 (executable)
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -59,9 +59,9 @@ namespace MipsISA {
         Addr level3() const
         { return MipsISA::PteAddr(addr >> PageShift); }
         Addr level2() const
-        { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
+        { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
         Addr level1() const
-        { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+        { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
     };
 
     // ITB/DTB page table entry

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 36cf76c67b0da29e15ab377b7bf153c37c130933..1985c0f43b29e0cd279fdfaa26401d9c36928a83 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -145,7 +145,7 @@ genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 {
     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 
-    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+    fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
            cc_val << cc_idx |
            bits(fcsr, cc_idx - 1, 0);
 

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index e201cef95260c155177d8c79d2188349ae40bd2b..9c189d164f61bdef98b7eff03543e87fc722218d 100644 (file)
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -546,7 +546,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
         doNormalFault(tc, trapType(), true);
         getHyperVector(tc, PC, NPC, 2);
     } else if (level == Hyperprivileged ||
-            level == Privileged && trapType() >= 384) {
+               (level == Privileged && trapType() >= 384)) {
         doNormalFault(tc, trapType(), true);
         getHyperVector(tc, PC, NPC, trapType());
     } else {

diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 38cde9a50c83babf9cb60d5efa3c3f62f5321d8d..f2a2327ee14be261c682be8c0b8b6599924a4156 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -314,10 +314,11 @@ let {{
     # are split into ones that are available in priv and hpriv, and
     # those that are only available in hpriv
     AlternateASIPrivFaultCheck = '''
-        if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
-                             !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
-                fault = new PrivilegedAction;
-        else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
+        if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
+             !AsiIsUnPriv((ASI)EXT_ASI)) ||
+            (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
+            fault = new PrivilegedAction;
+        else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
             fault = new PrivilegedAction;
     '''
 

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index defa33c516e76ff4c9dcc489c5560e465954d3f1..125ceba6925c204b4fd40094134ef68266e34f48 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -562,7 +562,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     asi = (ASI)req->getAsi();
     bool implicit = false;
     bool hpriv = bits(tlbdata,0,0);
-    bool unaligned = (vaddr & size-1);
+    bool unaligned = vaddr & (size - 1);
 
     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
             vaddr, size, asi);
@@ -801,8 +801,8 @@ handleIntRegAccess:
             return new PrivilegedAction;
     }
 
-    if (asi == ASI_SWVR_UDB_INTR_W && !write ||
-                    asi == ASI_SWVR_UDB_INTR_R && write) {
+    if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
+        (asi == ASI_SWVR_UDB_INTR_R && write)) {
         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
         return new DataAccessException;
     }
@@ -822,7 +822,7 @@ handleQueueRegAccess:
         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
         return new PrivilegedAction;
     }
-    if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
+    if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
         return new DataAccessException;
     }

diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc
index 31b705d798bbca9f329542c01c048dc0f15017ee..142e233dba802d954ba58a9368c1d5cfe18ab4f0 100644 (file)
--- a/src/arch/x86/emulenv.cc
+++ b/src/arch/x86/emulenv.cc
@@ -91,7 +91,7 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
     //Figure out what segment to use. This won't be entirely accurate since
     //the presence of a displacement is supposed to make the instruction
     //default to the data segment.
-    if (base != INTREG_RBP && base != INTREG_RSP ||
+    if ((base != INTREG_RBP && base != INTREG_RSP) ||
             0/*Has an immediate offset*/) {
         seg = SEGMENT_REG_DS;
         //Handle any segment override that might have been in the instruction

diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc
index 494c0b30309ba768b235e0efe84ca6c9830445ae..c7bfc3703789c017b9ae6be621aef50cc59b75a8 100644 (file)
--- a/src/arch/x86/insts/microop.cc
+++ b/src/arch/x86/insts/microop.cc
@@ -98,7 +98,7 @@ namespace X86ISA
           case ConditionTests::SxOF:
             return ccflags.sf ^ ccflags.of;
           case ConditionTests::SxOvZF:
-            return ccflags.sf ^ ccflags.of | ccflags.zf;
+            return (ccflags.sf ^ ccflags.of) | ccflags.zf;
           case ConditionTests::False:
             return false;
           case ConditionTests::NotECF:
@@ -131,7 +131,7 @@ namespace X86ISA
           case ConditionTests::NotSxOF:
             return !(ccflags.sf ^ ccflags.of);
           case ConditionTests::NotSxOvZF:
-            return !(ccflags.sf ^ ccflags.of | ccflags.zf);
+            return !((ccflags.sf ^ ccflags.of) | ccflags.zf);
         }
         panic("Unknown condition: %d\n", condition);
         return true;

diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc
index 1d415ffea38c20989092de2b3e1a718ecd4c7d59..9d60089e39e4ff9add9ef29c8eea1422e2c19c28 100644 (file)
--- a/src/arch/x86/predecoder.cc
+++ b/src/arch/x86/predecoder.cc
@@ -319,17 +319,17 @@ namespace X86ISA
         if (emi.mode.submode != SixtyFourBitMode &&
                 !csAttr.defaultSize) {
             //figure out 16 bit displacement size
-            if(modRM.mod == 0 && modRM.rm == 6 || modRM.mod == 2)
+            if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
                 displacementSize = 2;
-            else if(modRM.mod == 1)
+            else if (modRM.mod == 1)
                 displacementSize = 1;
             else
                 displacementSize = 0;
         } else {
             //figure out 32/64 bit displacement size
-            if(modRM.mod == 0 && modRM.rm == 5 || modRM.mod == 2)
+            if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
                 displacementSize = 4;
-            else if(modRM.mod == 1)
+            else if (modRM.mod == 1)
                 displacementSize = 1;
             else
                 displacementSize = 0;

diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index c27ab08ba47113a252961092366651a43dc57de0..3fda345cc7f15fe62628508a919d976d5eafaddd 100644 (file)
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -214,7 +214,7 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
     //If we need to fold over the index to match byte semantics, do that.
     //Otherwise, just strip off any extra bits and pass it through.
     if (reg & (1 << 6))
-        return (reg & ~(1 << 6) - 0x4);
+        return (reg & (~(1 << 6) - 0x4));
     else
         return (reg & ~(1 << 6));
 }

diff --git a/src/base/circlebuf.cc b/src/base/circlebuf.cc
index d42bb11c361e32be3a823e68a60ceb4119b4f155..06d0075b2dea6e67ecc3477ac8d9285623696fa0 100644 (file)
--- a/src/base/circlebuf.cc
+++ b/src/base/circlebuf.cc
@@ -208,7 +208,7 @@ CircleBuf::write(const char *b, int len)
         _rollover = true;
     }
 
-    if (old_start > old_stop && old_start < _stop ||
-        old_start < old_stop && _stop < old_stop)
+    if ((old_start > old_stop && old_start < _stop) ||
+        (old_start < old_stop && _stop < old_stop))
         _start = _stop + 1;
 }

diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index 227012e30a2435c5c131e751834e4d52b0063e47..c536fda519b843f13faf031d762dc76e52a1ccce 100644 (file)
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -197,9 +197,9 @@ roundDown(T val, int align)
 inline bool
 isHex(char c)
 {
-    return c >= '0' && c <= '9' ||
-        c >= 'A' && c <= 'F' ||
-        c >= 'a' && c <= 'f';
+    return (c >= '0' && c <= '9') ||
+        (c >= 'A' && c <= 'F') ||
+        (c >= 'a' && c <= 'f');
 }
 
 inline bool

diff --git a/src/base/random_mt.cc b/src/base/random_mt.cc
index 1492240ee93c49f8a19d2a42d1e16be90464c23e..6ea54ec0324ae2383b6c0aecf9a5bb847a307e5f 100644 (file)
--- a/src/base/random_mt.cc
+++ b/src/base/random_mt.cc
@@ -123,15 +123,15 @@ Random::genrand()
         int kk;
 
         for (kk = 0; kk < N - M; kk++) {
-            y = mt[kk] & UPPER_MASK | mt[kk+1] & LOWER_MASK;
+            y = (mt[kk] & UPPER_MASK) | (mt[kk+1] & LOWER_MASK);
             mt[kk] = mt[kk + M] ^ (y >> 1) ^ mag01[y & 0x1UL];
         }
         for (; kk < N - 1; kk++) {
-            y = mt[kk] & UPPER_MASK | mt[kk+1] & LOWER_MASK;
+            y = (mt[kk] & UPPER_MASK) | (mt[kk+1] & LOWER_MASK);
             mt[kk] = mt[kk + (M - N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
         }
 
-        y = mt[N - 1] & UPPER_MASK | mt[0] & LOWER_MASK;
+        y = (mt[N - 1] & UPPER_MASK) | (mt[0] & LOWER_MASK);
         mt[N - 1] = mt[M - 1] ^ (y >> 1) ^ mag01[y & 0x1UL];
 
         mti = 0;

diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index a018c4837aef295761159f46c27b42aa1f461e7d..6f40d92c859ff2d418a144825258f71c81b00093 100644 (file)
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -191,8 +191,8 @@ struct ScalarPrint
 void
 ScalarPrint::operator()(ostream &stream) const
 {
-    if (flags & nozero && value == 0.0 ||
-        flags & nonan && isnan(value))
+    if ((flags & nozero && value == 0.0) ||
+        (flags & nonan && isnan(value)))
         return;
 
     stringstream pdfstr, cdfstr;
@@ -474,8 +474,8 @@ DistPrint::operator()(ostream &stream) const
         print.flags = flags | __substat;
 
         for (int i = 0; i < size; ++i) {
-            if (flags & nozero && vec[i] == 0.0 ||
-                flags & nonan && isnan(vec[i]))
+            if ((flags & nozero && vec[i] == 0.0) ||
+                (flags & nonan && isnan(vec[i])))
                 continue;
 
             _min = i * bucket_size + min;

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index f06aee63468fbba4f3d7f9fa3753973cc8560d41..13a0962fd798d57e64243b0246c52cae9b5fc392 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -604,7 +604,7 @@ FullO3CPU<Impl>::suspendContext(int tid)
     DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
     bool deallocated = deallocateContext(tid, false, 1);
     // If this was the last thread then unschedule the tick event.
-    if (activeThreads.size() == 1 && !deallocated ||
+    if ((activeThreads.size() == 1 && !deallocated) ||
         activeThreads.size() == 0)
         unscheduleTickEvent();
     _status = Idle;

diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index 891fe17dad2388726ed80ed74ea4a7871cf75297..4477b5adcac1e147c0ce722a70dba9ab6e50d55e 100644 (file)
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -109,7 +109,7 @@ TsunamiCChip::read(PacketPtr pkt)
                   panic("TSDEV_CC_MTR not implemeted\n");
                    break;
               case TSDEV_CC_MISC:
-                  pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
+                  pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
                                      (pkt->req->getCpuNum() & 0x3));
                   break;
               case TSDEV_CC_AAR0:

diff --git a/src/dev/terminal.cc b/src/dev/terminal.cc
index 8c18e3bbcee63fc2df063a994b31ac9b50409329..fba0c61307faff21242f277fd518412e98ccc3ca 100644 (file)
--- a/src/dev/terminal.cc
+++ b/src/dev/terminal.cc
@@ -294,8 +294,7 @@ Terminal::out(char c)
     if (DTRACE(Terminal)) {
         static char last = '\0';
 
-        if (c != '\n' && c != '\r' ||
-            last != '\n' && last != '\r') {
+        if ((c != '\n' && c != '\r') || (last != '\n' && last != '\r')) {
             if (c == '\n' || c == '\r') {
                 int size = linebuf.size();
                 char *buffer = new char[size + 1];