add handle_trap

diff --git a/cpu.py b/cpu.py
index 6151294cef14c7b0e55e2ebac5ddd698532986c0..e0a6881c9248769e328e73ed1498ec4cf0bd49e3 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -294,7 +294,7 @@ class CPU(Module):
 
         # ecall/ebreak
         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
-                m.mcause.eq(Mux(decoder_immediate[0],
+                m.mcause.eq(Mux(dc.immediate[0],
                                 cause_machine_environment_call,
                                 cause_breakpoint))
               )
@@ -608,6 +608,9 @@ class CPU(Module):
         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
                                  branch_taken, misaligned_jump_target,
                                  csr_op_is_valid)
+
+        #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,
@@ -623,41 +626,6 @@ if __name__ == "__main__":
 
 """
 
-    task handle_trap;
-    begin
-        mstatus_mpie = mstatus_mie;
-        mstatus_mie = 0;
-        mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
-        if(fetch_action == `fetch_action_ack_trap) begin
-            mcause = `cause_instruction_access_fault;
-        end
-        else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
-            mcause = `cause_illegal_instruction;
-        end
-        else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
-            mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
-        end
-        else if((decode_action & `decode_action_load) != 0) begin
-            if(load_store_misaligned)
-                mcause = `cause_load_address_misaligned;
-            else
-                mcause = `cause_load_access_fault;
-        end
-        else if((decode_action & `decode_action_store) != 0) begin
-            if(load_store_misaligned)
-                mcause = `cause_store_amo_address_misaligned;
-            else
-                mcause = `cause_store_amo_access_fault;
-        end
-        else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
-            mcause = `cause_instruction_address_misaligned;
-        end
-        else begin
-            mcause = `cause_illegal_instruction;
-        end
-    end
-    endtask
-
     wire [11:0] csr_number = decoder_immediate;
     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);