fix sprset mtspr/mfspr pseudocode with wrong definition of

spr, not existent in the Power v3.0 spec.

https://bugs.libre-soc.org/show_bug.cgi?id=917#c54
works fine, required removal of hack in ISACaller to uppercase spr
to SPR

diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn
index ab1ace714a17c28871969ff11854800888e1c49f..f51cbbb66e372dfe180e768a65191678d1cb3771 100644 (file)
--- a/openpower/isa/sprset.mdwn
+++ b/openpower/isa/sprset.mdwn
@@ -31,11 +31,11 @@
 
 XFX-Form
 
-* mtspr SPR,RS
+* mtspr spr,RS
 
 Pseudo-code:
 
-    n <- spr[5:9] || spr[0:4]
+    n <- spr
     switch (n)
       case(13): see(Book_III_p974)
       case(808, 809, 810, 811):
@@ -55,11 +55,11 @@ Special Registers Altered:
 
 XFX-Form
 
-* mfspr RT,SPR
+* mfspr RT,spr
 
 Pseudo-code:
 
-    n <- spr[5:9] || spr[0:4]
+    n <- spr
     switch (n)
       case(129): see(Book_III_p975)
       case(808, 809, 810, 811):

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index 95c76fb77fbcbe99c45c0a41d39a7cf50a0636c9..2d3cdb4743d158f383f08fa8d32e8181117d4c57 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -824,6 +824,10 @@
          Immediate field that specifies signed versus
          unsigned conversion.
          Formats: X
+    spr (16:20,11:15)
+         Field used to specify a Special Purpose Register
+         for the mtspr and mfspr instructions.
+         Formats: XFX
     SPR (11:20)
          Field used to specify a Special Purpose Register
          for the mtspr and mfspr instructions.

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index e0caf47c7ffbdd06a3dfa802c2ba37745675a404..03ce7d6238a035d30ed9cb695836054184daa008 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -743,10 +743,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 assert regnum <= 7, "sigh, TODO, 128 CR fields"
                 val = (val & 0b11) | (regnum << 2)
             else:
-                if name == 'spr':
-                    sig = getattr(fields, name.upper())
-                else:
-                    sig = getattr(fields, name)
+                sig = getattr(fields, name)
                 val = yield sig
             # these are all opcode fields involved in index-selection of CR,
             # and need to do "standard" arithmetic.  CR[BA+32] for example