-;; Scheduling description for arch13.
+;; Scheduling description for z15.
;; Copyright (C) 2019 Free Software Foundation, Inc.
;; Contributed by Robin Dapp (rdapp@linux.ibm.com)
;; This file is part of GCC.
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-(define_attr "arch13_unit_fpd" ""
+(define_attr "z15_unit_fpd" ""
(cond [(eq_attr "mnemonic" "ddb,ddbr,deb,debr,dxbr,sqdb,sqdbr,sqeb,\
sqebr,sqxbr,vfddb,vfdsb,vfsqdb,vfsqsb,wfddb,wfdsb,wfdxb,wfsqdb,wfsqxb")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_unit_fxa" ""
+(define_attr "z15_unit_fxa" ""
(cond [(eq_attr "mnemonic" "a,afi,ag,agf,agfi,agfr,agh,aghi,aghik,\
agr,agrk,ah,ahi,ahik,ahy,al,alc,alcg,alcgr,alcr,alfi,alg,algf,algfi,algfr,\
alghsik,algr,algrk,alhsik,alr,alrk,aly,ar,ark,ay,bras,brasl,etnd,exrl,flogr,\
xgr,xgrk,xihf,xilf,xr,xrk,xy")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_unit_fxb" ""
+(define_attr "z15_unit_fxb" ""
(cond [(eq_attr "mnemonic" "agsi,algsi,alsi,asi,b,bc,bcr,bi,br,brcl,\
c,cfi,cg,cgf,cgfi,cgfr,cgfrl,cgh,cghi,cghrl,cghsi,cgit,cgr,cgrl,cgrt,ch,\
chi,chrl,chsi,chy,cit,cl,clfhsi,clfi,clfit,clg,clgf,clgfi,clgfr,clgfrl,\
vlvgp,vst,vstef,vsteg,vstl,vstrl,vstrlr,xi,xiy")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_unit_fxd" ""
+(define_attr "z15_unit_fxd" ""
(cond [(eq_attr "mnemonic" "dlgr,dlr,dr,dsgfr,dsgr")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_unit_lsu" ""
+(define_attr "z15_unit_lsu" ""
(cond [(eq_attr "mnemonic" "a,adb,aeb,ag,agf,agh,agsi,ah,ahy,al,alc,\
alcg,alg,algf,algsi,alsi,aly,asi,ay,c,cdb,ceb,cg,cgf,cgfrl,cgh,cghrl,cghsi,\
cgrl,ch,chrl,chsi,chy,cl,clc,clfhsi,clg,clgf,clgfrl,clghrl,clghsi,clgrl,\
vstef,vsteg,vstl,vstrl,vstrlr,x,xg,xi,xiy,xy")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_unit_vfu" ""
+(define_attr "z15_unit_vfu" ""
(cond [(eq_attr "mnemonic" "adb,adbr,adtr,aeb,aebr,axbr,axtr,cdb,\
cdbr,cdtr,ceb,cebr,cpsdr,cxbr,cxtr,ddtr,dxtr,fidbr,fidbra,fidtr,fiebr,\
fiebra,fixbr,fixbra,fixtr,lcdbr,lcebr,lcxbr,ldeb,ldebr,ldetr,le,ledbr,ledtr,\
wfmxb,wfnmaxb,wfnmsxb,wfsdb,wfssb,wfsxb,wldeb,wledb")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_cracked" ""
+(define_attr "z15_cracked" ""
(cond [(eq_attr "mnemonic" "bas,basr,cdfbr,cdftr,cdgbr,cdgtr,cdlfbr,\
cdlftr,cdlgbr,cdlgtr,cefbr,cegbr,celfbr,celgbr,cfdbr,cfebr,cfxbr,cgdbr,cgdtr,\
cgebr,cgxbr,cgxtr,chhsi,clfdbr,clfdtr,clfebr,clfxbr,clfxtr,clgdbr,clgdtr,\
rxsbg,stpq,vgef,vgeg,vscef,vsceg,vsteb,vsteh")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_expanded" ""
+(define_attr "z15_expanded" ""
(cond [(eq_attr "mnemonic" "cds,cdsg,cdsy,cxfbr,cxftr,cxgbr,cxgtr,\
cxlfbr,cxlftr,cxlgbr,cxlgtr,dl,dlg,dsg,dsgf,lam,lm,lmg,lmy,sldl,srda,srdl,\
stam,stm,stmg,stmy,tbegin,tbeginc")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_groupalone" ""
+(define_attr "z15_groupalone" ""
(cond [(eq_attr "mnemonic" "alc,alcg,alcgr,alcr,axbr,axtr,clc,cxbr,\
cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\
lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\
slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_endgroup" ""
+(define_attr "z15_endgroup" ""
(cond [(eq_attr "mnemonic" "bras,brasl,exrl,ipm")
(const_int 1)] (const_int 0)))
-(define_attr "arch13_groupoftwo" ""
+(define_attr "z15_groupoftwo" ""
(cond [(eq_attr "mnemonic" "vacccq,vacq,vfmadb,vfmasb,vfmsdb,vfmssb,\
vfnmadb,vfnmasb,vfnmsdb,vfnmssb,vgfmab,vgfmaf,vgfmag,vgfmah,vmaeb,vmaef,vmaeh,\
vmahb,vmahf,vmahh,vmalb,vmaleb,vmalef,vmaleh,vmalf,vmalhb,vmalhf,vmalhh,\
wfmadb,wfmasb,wfmaxb,wfmsdb,wfmssb,wfmsxb,wfnmaxb,wfnmsxb")
(const_int 1)] (const_int 0)))
-(define_insn_reservation "arch13_0" 0
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_0" 0
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "a,afi,ag,agfi,aghi,aghik,agr,agrk,ahi,ahik,al,\
alfi,alg,algf,algfi,algfr,alghsik,algr,algrk,alhsik,alr,alrk,aly,ar,ark,ay,\
b,bc,bcr,bi,br,bras,brasl,brcl,c,cfi,cg,cgfi,cghi,cghsi,cgit,cgr,cgrl,\
tmhh,tmhl,tml,tmlh,tmll,tmy,vlr,vlvgb,vlvgf,vlvgg,vlvgh,x,xg,xgr,xgrk,xihf,\
xilf,xr,xrk,xy")) "nothing")
-(define_insn_reservation "arch13_1" 1
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_1" 1
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "agf,agfr,agh,agsi,ah,ahy,algsi,alsi,asi,cgf,\
cgfr,cgfrl,cgh,cghrl,ch,chrl,chy,clm,clmy,cpsdr,laa,laag,lan,lang,lao,laog,\
lax,laxg,le,ler,ley,loc,locg,locghi,locgr,lochi,locr,mvghi,mvhhi,mvhi,mvi,\
wflcsb,wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,\
xiy")) "nothing")
-(define_insn_reservation "arch13_2" 2
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_2" 2
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cdb,cdbr,ceb,cebr,ear,ipm,l,lcbb,lcdbr,lcebr,ld,\
lde,ldy,lg,lgdr,lgrl,llc,llgc,llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lm,\
lmg,lmy,lndbr,lnebr,lpdbr,lpebr,lrl,ltdbr,ltebr,ly,popcnt,sar,tcdb,tceb,\
vlrepf,vlrepg,vlreph,vlrl,vlvgp,vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,\
wfcdb,wfcexbs,wfchexbs,wfchxbs,wfcsb")) "nothing")
-(define_insn_reservation "arch13_3" 3
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_3" 3
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cds,cdsy,mgh,mghi,mh,mhi,mhy,std,stdy,ste,stey,\
vcksm,vfeezbs,vfeezfs,vfeezhs,vgfmab,vgfmaf,vgfmag,vgfmah,vgfmb,vgfmf,vgfmg,\
vgfmh,vistrbs,vistrfs,vistrhs,vl,vlbb,vll,vlrlr,vmaeb,vmaef,vmaeh,vmahb,\
vmleb,vmlef,vmleh,vmlf,vmlhb,vmlhf,vmlhh,vmlhw,vmlob,vmlof,vmloh,vmob,vmof,\
vmoh,vsumb,vsumgf,vsumgh,vsumh,vsumqf,vsumqg,vtm")) "nothing")
-(define_insn_reservation "arch13_4" 4
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_4" 4
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "bas,basr,chhsi,clc,ex,lam,lcgfr,lngfr,lpgfr,lxr,\
lzxr,ms,msfi,msgf,msgfi,msgfr,msr,msy,mvc,nc,oc,ppa,rxsbg,tabort,tbegin,\
tbeginc,tend,vst,vstef,vsteg,vstl,vstrl,vstrlr,xc")) "nothing")
-(define_insn_reservation "arch13_5" 5
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_5" 5
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "adb,adbr,aeb,aebr,alc,alcg,alcgr,alcr,cs,csg,\
csy,fidbr,fidbra,fiebr,fiebra,ldeb,ldebr,ledbr,madbr,mdb,mdbr,meeb,meebr,\
msdbr,msrkc,sdb,sdbr,seb,sebr,slb,slbg,slbgr,slbr,stm,stmg,stmy,vfadb,vfasb,\
vfnmssb,vfsdb,vfssb,vldeb,vledb,vmslg,wfadb,wfasb,wfidb,wfisb,wflld,wfmadb,\
wfmasb,wfmdb,wfmsb,wfmsdb,wfmssb,wfsdb,wfssb,wldeb,wledb")) "nothing")
-(define_insn_reservation "arch13_6" 6
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_6" 6
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "msg,msgr,sfpc")) "nothing")
-(define_insn_reservation "arch13_7" 7
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_7" 7
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,ltdtr,msgrkc,sdtr,tdcdt,\
tdcet,vgef,vgeg")) "nothing")
-(define_insn_reservation "arch13_8" 8
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_8" 8
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cdsg,flogr,lpq,stpq,vsteb,vsteh")) "nothing")
-(define_insn_reservation "arch13_9" 9
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_9" 9
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cdfbr,cdgbr,cdlfbr,cdlgbr,cefbr,cegbr,celfbr,\
celgbr,cxfbr,cxgbr,cxlfbr,cxlgbr,m,madb,maeb,maebr,mfy,ml,mlr,mr,msdb,mseb,\
msebr,stam,wfaxb,wfixb,wfsxb")) "nothing")
-(define_insn_reservation "arch13_10" 10
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_10" 10
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "lxdb,lxdbr,lxeb,lxebr,vscef,vsceg")) "nothing")
-(define_insn_reservation "arch13_11" 11
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_11" 11
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cfdbr,cfebr,cgdbr,cgebr,clfdbr,clfebr,clgdbr,\
clgebr,mg,mgrk,mlg,mlgr")) "nothing")
-(define_insn_reservation "arch13_12" 12
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_12" 12
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cxbr,cxftr,cxlftr,cxtr,tcxb,tdcxt")) "nothing")
-(define_insn_reservation "arch13_13" 13
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_13" 13
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "axbr,axtr,fixbr,fixbra,fixtr,lcxbr,lnxbr,lpxbr,\
ltxbr,ltxtr,lxdtr,sxbr,sxtr")) "nothing")
-(define_insn_reservation "arch13_14" 14
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_14" 14
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cfxbr,cgxbr,clfxbr,clgxbr,ledtr")) "nothing")
-(define_insn_reservation "arch13_16" 16
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_16" 16
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cdftr,cdlftr")) "nothing")
-(define_insn_reservation "arch13_20" 20
- (and (eq_attr "cpu" "arch13")
+(define_insn_reservation "z15_20" 20
+ (and (eq_attr "cpu" "z15")
(eq_attr "mnemonic" "cdgtr,cdlgtr,cgdtr,cgxtr,clfdtr,clfxtr,clgdtr,\
clgxtr,cxgtr,cxlgtr,d,ddb,ddbr,ddtr,deb,debr,dl,dlg,dlgr,dlr,dr,dsg,dsgf,\
dsgfr,dsgr,dxbr,dxtr,efpc,mdtr,mxbr,mxtr,sqdb,sqdbr,sqeb,sqebr,sqxbr,vfddb,\
;; Processor type. This attribute must exactly match the processor_type
;; enumeration in s390.h.
-(define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,arch13"
+(define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15"
(const (symbol_ref "s390_tune_attr")))
(define_attr "cpu_facility"
- "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,arch13,vxe2"
+ "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2"
(const_string "standard"))
(define_attr "enabled" ""
(match_test "TARGET_VXE"))
(const_int 1)
- (and (eq_attr "cpu_facility" "arch13")
- (match_test "TARGET_ARCH13"))
+ (and (eq_attr "cpu_facility" "z15")
+ (match_test "TARGET_Z15"))
(const_int 1)
(and (eq_attr "cpu_facility" "vxe2")
;; Pipeline description for z14
(include "3906.md")
-;; Pipeline description for arch13
+;; Pipeline description for z15
(include "8561.md")
;; Predicates
(define_mode_iterator DD_DF [DF DD])
(define_mode_iterator TD_TF [TF TD])
-; 32 bit int<->fp conversion instructions are available since VXE2 (arch13).
+; 32 bit int<->fp conversion instructions are available since VXE2 (z15).
(define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")])
(define_mode_iterator VX_CONV_INT [DI (SI "TARGET_VXE2")])
stoc<g>%C1\t%3,%0
stoc<g>%D1\t%4,%0"
[(set_attr "op_type" "RRF,RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY")
- (set_attr "cpu_facility" "*,*,arch13,*,*,z13,z13,*,*")])
+ (set_attr "cpu_facility" "*,*,z15,*,*,z13,z13,*,*")])
;;
;;- Multiply instructions.
(and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
(match_operand:GPR 2 "general_operand" "")))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_ARCH13
+ "!TARGET_Z15
&& ! reload_completed
&& (GET_CODE (operands[0]) != MEM
/* Ensure that s390_logical_operator_ok_p will succeed even
(set (match_operand:GPR 0 "register_operand" "=d")
(ANDOR:GPR (not:GPR (match_dup 1))
(match_dup 2)))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
[(set_attr "op_type" "RRF")])
(match_operand:GPR 2 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
[(set_attr "op_type" "RRF")])
(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
(match_operand:GPR 2 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARCH13"
+ "TARGET_Z15"
"<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
[(set_attr "op_type" "RRF")])
(set (match_operand:GPR 0 "register_operand" "=d")
(ANDOR:GPR (not:GPR (match_dup 1))
(not:GPR (match_dup 2))))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
(not:GPR (match_operand:GPR 2 "register_operand" "d")))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
(not:GPR (match_operand:GPR 2 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARCH13"
+ "TARGET_Z15"
"n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
(set (match_operand:GPR 0 "register_operand" "=d")
(xor:GPR (not:GPR (match_dup 1))
(match_dup 2)))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"nx<GPR:g>rk\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
(match_operand:GPR 2 "register_operand" "d")))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=d"))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"nx<GPR:g>rk\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
(not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARCH13"
+ "TARGET_Z15"
"nx<GPR:g>rk\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
; Population count instruction
;
-(define_insn "*popcountdi_arch13_cc"
+(define_insn "*popcountdi_z15_cc"
[(set (reg CC_REGNUM)
(compare (popcount:DI (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(match_dup 1))]
- "TARGET_ARCH13 && s390_match_ccmode (insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode (insn, CCTmode)"
"popcnt\t%0,%1,8"
[(set_attr "op_type" "RRF")])
-(define_insn "*popcountdi_arch13_cconly"
+(define_insn "*popcountdi_z15_cconly"
[(set (reg CC_REGNUM)
(compare (popcount:DI (match_operand:DI 1 "register_operand" "d"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
- "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)"
"popcnt\t%0,%1,8"
[(set_attr "op_type" "RRF")])
-(define_insn "*popcountdi_arch13"
+(define_insn "*popcountdi_z15"
[(set (match_operand:DI 0 "register_operand" "=d")
(popcount:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARCH13"
+ "TARGET_Z15"
"popcnt\t%0,%1,8"
[(set_attr "op_type" "RRF")])
-; The pre-arch13 popcount instruction counts the bits of op1 in 8 byte
+; The pre-z15 popcount instruction counts the bits of op1 in 8 byte
; portions and stores the result in the corresponding bytes in op0.
(define_insn "*popcount<mode>_z196"
[(set (match_operand:INT 0 "register_operand" "=d")
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z196"
{
- if (!TARGET_ARCH13)
+ if (!TARGET_Z15)
{
emit_insn (gen_popcountdi2_z196 (operands[0], operands[1]));
DONE;
; popcount always counts on the full 64 bit. With the z196 version
; counting bits per byte we just ignore the upper 4 bytes. With the
-; arch13 version we have to zero out the upper 32 bits first.
+; z15 version we have to zero out the upper 32 bits first.
(define_expand "popcountsi2"
[(set (match_dup 2)
(zero_extend:DI (match_operand:SI 1 "register_operand")))
(subreg:SI (match_dup 3) 4))]
"TARGET_Z196"
{
- if (!TARGET_ARCH13)
+ if (!TARGET_Z15)
{
emit_insn (gen_popcountsi2_z196 (operands[0], operands[1]));
DONE;
(subreg:HI (match_dup 3) 6))]
"TARGET_Z196"
{
- if (!TARGET_ARCH13)
+ if (!TARGET_Z15)
{
emit_insn (gen_popcounthi2_z196 (operands[0], operands[1]));
DONE;
; For popcount on a single byte the old z196 style popcount
; instruction is ideal. Since it anyway does a byte-wise popcount we
; just use it instead of zero extending the QImode input to DImode and
-; using the arch13 popcount variant.
+; using the z15 popcount variant.
(define_expand "popcountqi2"
[; popcnt op0, op1
(parallel [(set (match_operand:QI 0 "register_operand" "")
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