vendor: yosys is a required tool for all Verilog-based flows.
authorwhitequark <cz@m-labs.hk>
Thu, 10 Oct 2019 14:38:09 +0000 (14:38 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 10 Oct 2019 14:38:09 +0000 (14:38 +0000)
nmigen/vendor/lattice_ecp5.py
nmigen/vendor/lattice_ice40.py
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_spartan_3_6.py

index 8852fb82eab61d8a69f6440ef9e352c5375496fe..e6d447a74750c477ac5c4f0ab70480d56c6b7b21 100644 (file)
@@ -165,6 +165,7 @@ class LatticeECP5Platform(TemplatedPlatform):
     # Diamond templates
 
     _diamond_required_tools = [
+        "yosys",
         "pnmainc",
         "ddtcmd"
     ]
index cc395c081bb353ebb09e48a4687de4dfc9d3153f..d3fa8c71e04719688e6cbc87966aef73897460b8 100644 (file)
@@ -170,6 +170,7 @@ class LatticeICE40Platform(TemplatedPlatform):
     # iCECube2 templates
 
     _icecube2_required_tools = [
+        "yosys",
         "synthesis",
         "synpwrap",
         "tclsh",
index 0d64e3e939d374e6a7636f3e3e46c0e22655f157..d26c438a1bfc5fda7f416bf3e5cc1ff76174e01b 100644 (file)
@@ -51,7 +51,10 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
     package = abstractproperty()
     speed   = abstractproperty()
 
-    required_tools = ["vivado"]
+    required_tools = [
+        "yosys",
+        "vivado"
+    ]
 
     file_templates = {
         **TemplatedPlatform.build_script_templates,
index 65f4a0a5ad3be36b5e628cedf6236547f962e830..929b81d022035f0f990c32d7e7fd641049fc3c01 100644 (file)
@@ -59,6 +59,7 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
     speed   = abstractproperty()
 
     required_tools = [
+        "yosys",
         "xst",
         "ngdbuild",
         "map",