re PR c++/47688 ([C++0x] Segfault when assigning lambda to std::function variable)

Fix PR 47688

2011-03-18  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/47668
	gcc/
	* config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c'
	in the output template.
	gcc/testsuite/
	* gcc.target/arm/pr47688.c: New.

From-SVN: r171000

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d3f2eeffb7a2f94c6aeeeadd0423d32a4c0726ed..572309cdd89319e41ed014ba5632d8472aba7ddb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-03-15  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+       PR target/47668
+       * config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c'
+       in the output template.
+
 2011-03-15  Richard Guenther  <rguenther@suse.de>
 
        PR middle-end/47650

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 6f31e6211b4900eb12f53615328cb38cd5c094b0..b0f31f51934e5743da5db0787d703b09de10a883 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -10580,13 +10580,15 @@
   [(set_attr "conds" "clob")]
 )
 
+;; We only care about the lower 16 bits of the constant 
+;; being inserted into the upper 16 bits of the register.
 (define_insn "*arm_movtas_ze" 
   [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
                    (const_int 16)
                    (const_int 16))
         (match_operand:SI 1 "const_int_operand" ""))]
   "arm_arch_thumb2"
-  "movt%?\t%0, %c1"
+  "movt%?\t%0, %L1"
  [(set_attr "predicable" "yes")
    (set_attr "length" "4")]
 )

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 753f90045b6803be1ad69650dbf914fb727ed985..289736606582b780ec29caf03dadf633581ea53c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-15  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+       PR target/47688
+       * gcc.target/arm/pr47688.c: New.
+
 2011-03-15  Richard Guenther  <rguenther@suse.de>
 
        PR middle-end/47650

diff --git a/gcc/testsuite/gcc.target/arm/pr47688.c b/gcc/testsuite/gcc.target/arm/pr47688.c
new file mode 100644 (file)
index 0000000..2236769
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr47688.c
@@ -0,0 +1,26 @@
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler-not "-32768" } } */
+
+typedef union
+{
+  unsigned long int u_32_value;
+  struct 
+  {
+    unsigned short int u_16_value_0;
+    unsigned short int u_16_value_1;
+  } u_16_values;
+} my_union;
+
+
+unsigned long int Test(const unsigned short int wXe)
+{
+  my_union dwCalcVal;
+  
+  dwCalcVal.u_16_values.u_16_value_0=wXe;
+  dwCalcVal.u_16_values.u_16_value_1=0x8000u;
+
+  dwCalcVal.u_32_value /=3;
+  
+  return (dwCalcVal.u_32_value);
+}