cpu: Move packet deallocation to recvTimingResp in the O3 CPU

Move the packet deallocations in the O3 CPU so that the completeDataAccess
deals only with the LSQ specific parts and the generic recvTimingResp frees the
packet in all other cases.

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 5d50b98ea089789c001d94f80054e66a8a45e410..2c9c6eb82b78a9d053921815f6881e081a5ebd2c 100644 (file)
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -347,6 +347,8 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt)
         DPRINTF(LSQ, "Got error packet back for address: %#X\n",
                 pkt->getAddr());
     thread[pkt->req->threadId()].completeDataAccess(pkt);
+    delete pkt->req;
+    delete pkt;
     return true;
 }
 

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 887e971b4c9406a2265f3fee9abd00369c4a78b3..0cc412811005b9e146bf5d257adda41857ba8395 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -105,15 +105,11 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
                 "blocked split load recieved. Ignoring.\n", inst->seqNum);
         delete state;
-        delete pkt->req;
-        delete pkt;
         return;
     }
 
     // If this is a split access, wait until all packets are received.
     if (TheISA::HasUnalignedMemAcc && !state->complete()) {
-        delete pkt->req;
-        delete pkt;
         return;
     }
 
@@ -142,8 +138,6 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
     cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
 
     delete state;
-    delete pkt->req;
-    delete pkt;
 }
 
 template <class Impl>