arm: Teach gem5 to recognize the gem5 semihosting immediate values.

These give access to the gem5 extension calls, currently only the pseudo
ops.

Change-Id: I60ece82f1f084791971a2de0b54be2f0d9da243e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27246
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 9cdc1f926ad7446e29caf45fae48e7c346144155..14d1c55723331989a723650249e23dd227bebe8d 100644 (file)
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -98,6 +98,7 @@ output exec {{
 #include "arch/arm/isa.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/pauth_helpers.hh"
+#include "arch/arm/semihosting.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/memhelpers.hh"
 #include "base/condcodes.hh"

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index e8935b842777cd6d2a8fe631a635b4509df9acf5..b2f459158ab26aa51713d2c73d40423ee18d1726 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,10 +40,14 @@ let {{
     svcCode = '''
     ThreadContext *tc = xc->tcBase();
 
-    const auto semihost_imm = Thumb? 0xAB : 0x123456;
-
-    if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
+    bool have_semi = ArmSystem::haveSemihosting(tc);
+    if (have_semi && Thumb && imm == ArmSemihosting::T32Imm) {
+        // Enable gem5 extensions since we can't distinguish in thumb.
+        ArmSystem::callSemihosting32(tc, true);
+    } else if (have_semi && imm == ArmSemihosting::A32Imm) {
         ArmSystem::callSemihosting32(tc);
+    } else if (have_semi && imm == ArmSemihosting::Gem5Imm) {
+        ArmSystem::callSemihosting32(tc, true);
     } else {
         fault = std::make_shared<SupervisorCall>(machInst, imm);
     }

diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index e2cfb41dd2c4c6608f0abfa435851771ad417c17..656a23445ff8b4b22093c52670bc3e70474ec4d3 100644 (file)
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -185,8 +185,11 @@ let {{
 
     hltCode = '''
     ThreadContext *tc = xc->tcBase();
-    if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) {
+    bool have_semi = ArmSystem::haveSemihosting(tc);
+    if (imm == ArmSemihosting::A64Imm && have_semi) {
         ArmSystem::callSemihosting64(tc);
+    } else if (imm == ArmSemihosting::Gem5Imm && have_semi) {
+        ArmSystem::callSemihosting64(tc, true);
     } else {
         // HLT instructions aren't implemented, so treat them as undefined
         // instructions.

diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 83d41fd42572bec4808f4a39b13a974e2c986bc4..e9dc984e20e07c9261fbe7479763696d26e90339 100644 (file)
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -73,6 +73,17 @@ class ArmSemihosting : public SimObject
 {
   public:
 
+    enum {
+        // Standard ARM immediate values which trigger semihosting.
+        T32Imm = 0xAB,
+        A32Imm = 0x123456,
+        A64Imm = 0xF000,
+
+        // The immediate value which enables gem5 semihosting calls. Use the
+        // standard value for thumb.
+        Gem5Imm = 0x5D57
+    };
+
     static PortProxy &portProxy(ThreadContext *tc);
 
     struct AbiBase