periph.base: use bridge granularity as CSR bus data width.

diff --git a/lambdasoc/periph/base.py b/lambdasoc/periph/base.py
index 84c3452c4f597dca6968a103b3921bea0280959c..b023ad55cd37cfcabefa297ddb51885218e83dce 100644 (file)
--- a/lambdasoc/periph/base.py
+++ b/lambdasoc/periph/base.py
@@ -313,7 +313,7 @@ class PeripheralBridge(Elaboratable):
         for bank, bank_addr, bank_alignment in periph.iter_csr_banks():
             if bank_alignment is None:
                 bank_alignment = alignment
-            csr_mux = csr.Multiplexer(addr_width=1, data_width=8, alignment=bank_alignment)
+            csr_mux = csr.Multiplexer(addr_width=1, data_width=granularity, alignment=bank_alignment)
             for elem, elem_addr, elem_alignment in bank.iter_csr_regs():
                 if elem_alignment is None:
                     elem_alignment = alignment