(no commit message)

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index 442d39526c4f4383ccbb8291e07830b7367988d1..1f210c5b2e268c7fa3bfc7178d7a89020fb83602 100644 (file)
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -303,9 +303,15 @@ the sequential conceptual overlap between **all** registers, as
 ultimately the regfile must be considered arbitrarily-byte-addressable
 just like any Memory, and therefore writing to
 half-word element `e4` starting from **GPR(2)** actually wrote to
-half-word element `e0` of GPR(3).
-
-     | B0     | B1    | B2    | B3    | B4    |    B5 |    B6 |    B7   |
-     | r0.b[7] r0.b[5] r0.b[4] r0.b[3] r0.b[2] r0.b[1] r0.b[6] r0.b[0]  |
-     |        H0      |      H1       |      H2       |      H3         |
-     | r0.b[7] r0.b[5] r0.b[4] r0.b[3] r0.b[2] r0.b[1] r0.b[6] r0.b[0]  |
+half-word element `e0` of GPR(3):
+
+ 
+
+    | B0     | B1    | B2    | B3    | B4    |    B5 |    B6 |    B7   |
+    |        H0      |      H1       |      H2       |      H3         |
+    |                W0              |               W1                |
+    |                                D0                                |
+    | r0.b[7] r0.b[5] r0.b[4] r0.b[3] r0.b[2] r0.b[1] r0.b[6] r0.b[0]  |
+    |     r0.s[3]        r0.s[2]         r0.s[1]         r0.s[0]       |
+    |             r0.i[1]                         r0.i[1]              |
+    |                              r0.l[0]                             |