Constant driven signals are also an input to submodules

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 707bc26b37a19f8d907d364647c0fa7328c82e06..a1fac9b7914ff77ca78256cc35d8d0dc62260b8f 100644 (file)
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -33,7 +33,7 @@ struct SubmodWorker
        CellTypes ct;
        RTLIL::Design *design;
        RTLIL::Module *module;
-       pool<Wire*> outputs;
+       pool<Wire*> constants, outputs;
 
        bool copy_mode;
        std::string opt_name;
@@ -125,7 +125,7 @@ struct SubmodWorker
                        RTLIL::Wire *wire = it.first;
                        wire_flags_t &flags = it.second;
 
-                       if (wire->port_input)
+                       if (wire->port_input || constants.count(wire))
                                flags.is_ext_driven = true;
                        if (wire->port_output || outputs.count(wire))
                                flags.is_ext_used = true;
@@ -235,6 +235,14 @@ struct SubmodWorker
                                outputs.insert(c.wire);
                        }
                }
+               for (auto wire : module->wires()) {
+                       auto sig = sigmap(wire);
+                       for (auto c : sig.chunks()) {
+                               if (c.wire)
+                                       continue;
+                               constants.insert(wire);
+                       }
+               }
 
                if (opt_name.empty())
                {