ARM: Fix up the implmentation of the mrs instruction.

diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 20b544a7ca471ae944859c281e33a263f356c538..cd13fa4209989f5aeb6612e90ef67ead62a2d5c3 100644 (file)
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -110,7 +110,9 @@ format DataOp {
             }
             1: decode MISC_OPCODE {
                 0x0: decode OPCODE {
-                    0x8: PredOp::mrs_cpsr({{ Rd = Cpsr | CondCodes; }});
+                    0x8: PredOp::mrs_cpsr({{
+                        Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
+                    }});
                     0x9: PredOp::msr_cpsr({{
                         //assert(!RN<1:0>);
                         if (OPCODE_18) {
@@ -120,7 +122,7 @@ format DataOp {
                             CondCodes = mbits(Rm, 31,27);
                         }
                     }});
-                    0xa: PredOp::mrs_spsr({{ Rd = 0; // should be SPSR}});
+                    0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
                     0xb: WarnUnimpl::msr_spsr();
                 }
                 0x1: decode OPCODE {