if (!r300->ctx)
goto fail;
- r300->cs = rws->cs_create(r300->ctx, RING_GFX, r300_flush_callback, r300, NULL);
+ r300->cs = rws->cs_create(r300->ctx, RING_GFX, r300_flush_callback, r300);
if (r300->cs == NULL)
goto fail;
}
r300->flush_counter++;
- r300->rws->cs_flush(r300->cs, flags, fence, 0);
+ r300->rws->cs_flush(r300->cs, flags, fence);
r300->dirty_hw = 0;
/* New kitchen sink, baby. */
* and we cannot emit an empty CS. Let's write to some reg. */
CS_LOCALS(r300);
OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0);
- r300->rws->cs_flush(r300->cs, flags, fence, 0);
+ r300->rws->cs_flush(r300->cs, flags, fence);
} else {
/* Even if hw is not dirty, we should at least reset the CS in case
* the space checking failed for the first draw operation. */
- r300->rws->cs_flush(r300->cs, flags, NULL, 0);
+ r300->rws->cs_flush(r300->cs, flags, NULL);
}
}
/* The number of dwords all the dirty states would take. */
mask = ctx->dirty_atoms;
- while (mask != 0) {
+ while (mask != 0)
num_dw += ctx->atoms[u_bit_scan64(&mask)]->num_dw;
- if (ctx->screen->b.trace_bo) {
- num_dw += R600_TRACE_CS_DWORDS;
- }
- }
/* The upper-bound of how much space a draw command would take. */
num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
- if (ctx->screen->b.trace_bo) {
- num_dw += R600_TRACE_CS_DWORDS;
- }
}
/* Count in queries_suspend. */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
/* Flush the CS. */
- ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++);
+ ctx->b.ws->cs_flush(cs, flags, fence);
r600_begin_new_cs(ctx);
}
}
rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
- r600_context_gfx_flush, rctx,
- rscreen->b.trace_bo ?
- rscreen->b.trace_bo->buf : NULL);
+ r600_context_gfx_flush, rctx);
rctx->b.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
/* the number of CS dwords for flushing and drawing */
#define R600_MAX_FLUSH_CS_DWORDS 16
#define R600_MAX_DRAW_CS_DWORDS 58
-#define R600_TRACE_CS_DWORDS 7
#define R600_MAX_USER_CONST_BUFFERS 13
#define R600_MAX_DRIVER_CONST_BUFFERS 3
r600_set_atom_dirty(rctx, atom, true);
}
-void r600_trace_emit(struct r600_context *rctx);
-
static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
{
atom->emit(&rctx->b, atom);
r600_set_atom_dirty(rctx, atom, false);
- if (rctx->screen->b.trace_bo) {
- r600_trace_emit(rctx);
- }
}
static inline void r600_set_cso_state(struct r600_context *rctx,
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT);
}
- if (rctx->screen->b.trace_bo) {
- r600_trace_emit(rctx);
- }
-
/* Set the depth buffer as dirty. */
if (rctx->framebuffer.state.zsbuf) {
struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
}
-
-void r600_trace_emit(struct r600_context *rctx)
-{
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
- uint64_t va;
- uint32_t reloc;
-
- va = rscreen->b.trace_bo->gpu_address;
- reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rscreen->b.trace_bo,
- RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
- radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
- radeon_emit(cs, va & 0xFFFFFFFFUL);
- radeon_emit(cs, (va >> 32UL) & 0xFFUL);
- radeon_emit(cs, cs->cdw);
- radeon_emit(cs, rscreen->b.cs_count);
- radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, reloc);
-}
struct radeon_winsys_cs *cs = rctx->dma.cs;
if (cs->cdw)
- rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence, 0);
+ rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
if (fence)
rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
}
if (rscreen->info.has_sdma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
r600_flush_dma_ring,
- rctx, NULL);
+ rctx);
rctx->dma.flush = r600_flush_dma_ring;
}
{ "tex", DBG_TEX, "Print texture info" },
{ "compute", DBG_COMPUTE, "Print compute info" },
{ "vm", DBG_VM, "Print virtual addresses when creating resources" },
- { "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
{ "info", DBG_INFO, "Print driver information" },
/* shaders */
pipe_mutex_init(rscreen->aux_context_lock);
pipe_mutex_init(rscreen->gpu_load_mutex);
- if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
- rscreen->info.drm_major == 3) &&
- (rscreen->debug_flags & DBG_TRACE_CS)) {
- rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
- PIPE_BIND_CUSTOM,
- PIPE_USAGE_STAGING,
- 4096);
- if (rscreen->trace_bo) {
- rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->buf, NULL,
- PIPE_TRANSFER_UNSYNCHRONIZED);
- }
- }
-
if (rscreen->debug_flags & DBG_INFO) {
printf("pci_id = 0x%x\n", rscreen->info.pci_id);
printf("family = %i (%s)\n", rscreen->info.family,
pipe_mutex_destroy(rscreen->aux_context_lock);
rscreen->aux_context->destroy(rscreen->aux_context);
- if (rscreen->trace_bo)
- pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
-
rscreen->ws->destroy(rscreen->ws);
FREE(rscreen);
}
/* gap - reuse */
#define DBG_COMPUTE (1 << 2)
#define DBG_VM (1 << 3)
-#define DBG_TRACE_CS (1 << 4)
+/* gap - reuse */
/* shader logging */
#define DBG_FS (1 << 5)
#define DBG_VS (1 << 6)
struct pipe_context *aux_context;
pipe_mutex aux_context_lock;
- struct r600_resource *trace_bo;
- uint32_t *trace_ptr;
- unsigned cs_count;
-
/* This must be in the screen, because UE4 uses one context for
* compilation and another one for rendering.
*/
/* flush IB to the hardware */
static void flush(struct ruvd_decoder *dec)
{
- dec->ws->cs_flush(dec->cs, RADEON_FLUSH_ASYNC, NULL, 0);
+ dec->ws->cs_flush(dec->cs, RADEON_FLUSH_ASYNC, NULL);
}
/* add a new set register command to the IB */
dec->stream_handle = rvid_alloc_stream_handle();
dec->screen = context->screen;
dec->ws = ws;
- dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL, NULL);
+ dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL);
if (!dec->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
*/
static void flush(struct rvce_encoder *enc)
{
- enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL, 0);
+ enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL);
enc->task_info_idx = 0;
enc->bs_idx = 0;
}
enc->screen = context->screen;
enc->ws = ws;
- enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc, NULL);
+ enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc);
if (!enc->cs) {
RVID_ERR("Can't get command submission context.\n");
goto error;
* \param ring_type The ring type (GFX, DMA, UVD)
* \param flush Flush callback function associated with the command stream.
* \param user User pointer that will be passed to the flush callback.
- * \param trace_buf Trace buffer when tracing is enabled
*/
struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
- void *flush_ctx,
- struct pb_buffer *trace_buf);
+ void *flush_ctx);
/**
* Destroy a command stream.
* \param flags, RADEON_FLUSH_ASYNC or 0.
* \param fence Pointer to a fence. If non-NULL, a fence is inserted
* after the CS and is returned through this parameter.
- * \param cs_trace_id A unique identifier of the cs, used for tracing.
*/
void (*cs_flush)(struct radeon_winsys_cs *cs,
unsigned flags,
- struct pipe_fence_handle **fence,
- uint32_t cs_trace_id);
+ struct pipe_fence_handle **fence);
/**
* Return TRUE if a buffer is referenced by a command stream.
}
/* Flush the CS. */
- ws->cs_flush(cs, flags, &ctx->last_gfx_fence,
- ctx->screen->b.cs_count++);
+ ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
if (fence)
ws->fence_reference(fence, ctx->last_gfx_fence);
sctx->b.b.create_video_buffer = vl_video_buffer_create;
}
- sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
- sctx, sscreen->b.trace_bo ?
- sscreen->b.trace_bo->buf : NULL);
+ sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
+ si_context_gfx_flush, sctx);
sctx->b.gfx.flush = si_context_gfx_flush;
/* Border colors. */
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
- void *flush_ctx,
- struct pb_buffer *trace_buf)
+ void *flush_ctx)
{
struct amdgpu_ctx *ctx = (struct amdgpu_ctx*)rwctx;
struct amdgpu_cs *cs;
static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
unsigned flags,
- struct pipe_fence_handle **fence,
- uint32_t cs_trace_id)
+ struct pipe_fence_handle **fence)
{
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ctx->ws;
noinst_LTLIBRARIES = libradeonwinsys.la
libradeonwinsys_la_SOURCES = $(C_SOURCES)
-
-EXTRA_DIST = $(TOOLS_HDR)
radeon_drm_bo.c \
radeon_drm_bo.h \
radeon_drm_cs.c \
- radeon_drm_cs_dump.c \
radeon_drm_cs.h \
radeon_drm_public.h \
radeon_drm_surface.c \
radeon_drm_winsys.c \
radeon_drm_winsys.h
-
-TOOLS_HDR := \
- radeon_ctx.h
+++ /dev/null
-/*
- * Copyright 2011 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Jérôme Glisse
- */
-#ifndef RADEON_CTX_H
-#define RADEON_CTX_H
-
-#define _FILE_OFFSET_BITS 64
-#include <sys/mman.h>
-
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <string.h>
-#include "xf86drm.h"
-#include "radeon_drm.h"
-
-struct ctx {
- int fd;
-};
-
-struct bo {
- uint32_t handle;
- uint32_t alignment;
- uint64_t size;
- uint64_t va;
- void *ptr;
-};
-
-static void ctx_init(struct ctx *ctx)
-{
- ctx->fd = drmOpen("radeon", NULL);
- if (ctx->fd < 0) {
- fprintf(stderr, "failed to open radeon drm device file\n");
- exit(-1);
- }
-}
-
-static void bo_wait(struct ctx *ctx, struct bo *bo)
-{
- struct drm_radeon_gem_wait_idle args;
- void *ptr;
- int r;
-
- /* Zero out args to make valgrind happy */
- memset(&args, 0, sizeof(args));
- args.handle = bo->handle;
- do {
- r = drmCommandWrite(ctx->fd, DRM_RADEON_GEM_WAIT_IDLE, &args, sizeof(args));
- } while (r == -EBUSY);
-}
-
-
-static void ctx_cs(struct ctx *ctx, uint32_t *cs, uint32_t cs_flags[2], unsigned ndw,
- struct bo **bo, uint32_t *bo_relocs, unsigned nbo)
-{
- struct drm_radeon_cs args;
- struct drm_radeon_cs_chunk chunks[3];
- uint64_t chunk_array[3];
- unsigned i;
- int r;
-
- /* update handle */
- for (i = 0; i < nbo; i++) {
- bo_relocs[i*4+0] = bo[i]->handle;
- }
-
- args.num_chunks = 2;
- if (cs_flags[0] || cs_flags[1]) {
- /* enable RADEON_CHUNK_ID_FLAGS */
- args.num_chunks = 3;
- }
- args.chunks = (uint64_t)(uintptr_t)chunk_array;
- chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
- chunks[0].length_dw = ndw;
- chunks[0].chunk_data = (uintptr_t)cs;
- chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
- chunks[1].length_dw = nbo * 4;
- chunks[1].chunk_data = (uintptr_t)bo_relocs;
- chunks[2].chunk_id = RADEON_CHUNK_ID_FLAGS;
- chunks[2].length_dw = 2;
- chunks[2].chunk_data = (uintptr_t)cs_flags;
- chunk_array[0] = (uintptr_t)&chunks[0];
- chunk_array[1] = (uintptr_t)&chunks[1];
- chunk_array[2] = (uintptr_t)&chunks[2];
-
- fprintf(stderr, "emiting cs %ddw with %d bo\n", ndw, nbo);
- r = drmCommandWriteRead(ctx->fd, DRM_RADEON_CS, &args, sizeof(args));
- if (r) {
- fprintf(stderr, "cs submission failed with %d\n", r);
- return;
- }
-}
-
-static void bo_map(struct ctx *ctx, struct bo *bo)
-{
- struct drm_radeon_gem_mmap args;
- void *ptr;
- int r;
-
- /* Zero out args to make valgrind happy */
- memset(&args, 0, sizeof(args));
- args.handle = bo->handle;
- args.offset = 0;
- args.size = (uint64_t)bo->size;
- r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_MMAP, &args, sizeof(args));
- if (r) {
- fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", bo, bo->handle, r);
- exit(-1);
- }
- ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, ctx->fd, args.addr_ptr);
- if (ptr == MAP_FAILED) {
- fprintf(stderr, "%s failed to map bo\n", __func__);
- exit(-1);
- }
- bo->ptr = ptr;
-}
-
-static void bo_va(struct ctx *ctx, struct bo *bo)
-{
- struct drm_radeon_gem_va args;
- int r;
-
- args.handle = bo->handle;
- args.vm_id = 0;
- args.operation = RADEON_VA_MAP;
- args.flags = RADEON_VM_PAGE_READABLE | RADEON_VM_PAGE_WRITEABLE | RADEON_VM_PAGE_SNOOPED;
- args.offset = bo->va;
- r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_VA, &args, sizeof(args));
- if (r && args.operation == RADEON_VA_RESULT_ERROR) {
- fprintf(stderr, "radeon: Failed to allocate virtual address for buffer:\n");
- fprintf(stderr, "radeon: size : %d bytes\n", bo->size);
- fprintf(stderr, "radeon: alignment : %d bytes\n", bo->alignment);
- fprintf(stderr, "radeon: va : 0x%016llx\n", (unsigned long long)bo->va);
- exit(-1);
- }
-}
-
-static struct bo *bo_new(struct ctx *ctx, unsigned ndw, uint32_t *data, uint64_t va, uint32_t alignment)
-{
- struct drm_radeon_gem_create args;
- struct bo *bo;
- int r;
-
- bo = calloc(1, sizeof(*bo));
- if (bo == NULL) {
- fprintf(stderr, "failed to malloc bo struct\n");
- exit(-1);
- }
- bo->size = ndw * 4ULL;
- bo->va = va;
- bo->alignment = alignment;
-
- args.size = bo->size;
- args.alignment = bo->alignment;
- args.initial_domain = RADEON_GEM_DOMAIN_GTT;
- args.flags = 0;
- args.handle = 0;
-
- r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_CREATE, &args, sizeof(args));
- bo->handle = args.handle;
- if (r) {
- fprintf(stderr, "Failed to allocate :\n");
- fprintf(stderr, " size : %d bytes\n", bo->size);
- fprintf(stderr, " alignment : %d bytes\n", bo->alignment);
- free(bo);
- exit(-1);
- }
-
- if (data) {
- bo_map(ctx, bo);
- memcpy(bo->ptr, data, bo->size);
- }
-
- if (va) {
- bo_va(ctx, bo);
- }
-
- return bo;
-}
-
-
-#endif
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
- void *flush_ctx,
- struct pb_buffer *trace_buf)
+ void *flush_ctx)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)ctx;
struct radeon_drm_cs *cs;
cs->ws = ws;
cs->flush_cs = flush;
cs->flush_data = flush_ctx;
- cs->trace_buf = (struct radeon_bo*)trace_buf;
if (!radeon_init_cs_context(&cs->csc1, cs->ws)) {
FREE(cs);
}
}
- if (cs->trace_buf) {
- radeon_dump_cs_on_lockup(cs, csc);
- }
-
for (i = 0; i < csc->crelocs; i++)
p_atomic_dec(&csc->relocs_bo[i].bo->num_active_ioctls);
static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
unsigned flags,
- struct pipe_fence_handle **fence,
- uint32_t cs_trace_id)
+ struct pipe_fence_handle **fence)
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_cs_context *tmp;
cs->csc = cs->cst;
cs->cst = tmp;
- cs->cst->cs_trace_id = cs_trace_id;
-
/* If the CS is not empty or overflowed, emit it in a separate thread. */
if (cs->base.cdw && cs->base.cdw <= cs->base.max_dw && !debug_get_option_noop()) {
unsigned i, crelocs;
uint64_t chunk_array[3];
uint32_t flags[2];
- uint32_t cs_trace_id;
-
/* Buffers. */
unsigned nrelocs;
unsigned crelocs;
void *flush_data;
pipe_semaphore flush_completed;
- struct radeon_bo *trace_buf;
};
int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo);
void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws);
void radeon_drm_cs_emit_ioctl_oneshot(struct radeon_drm_cs *cs, struct radeon_cs_context *csc);
-void radeon_dump_cs_on_lockup(struct radeon_drm_cs *cs, struct radeon_cs_context *csc);
-
#endif
+++ /dev/null
-/*
- * Copyright © 2013 Jérôme Glisse
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
- * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- */
-/*
- * Authors:
- * Jérôme Glisse <jglisse@redhat.com>
- */
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <inttypes.h>
-#include <xf86drm.h>
-#include "radeon_drm_cs.h"
-#include "radeon_drm_bo.h"
-
-#define RADEON_CS_DUMP_AFTER_MS_TIMEOUT 500
-
-void radeon_dump_cs_on_lockup(struct radeon_drm_cs *cs, struct radeon_cs_context *csc)
-{
- struct drm_radeon_gem_busy args;
- FILE *dump;
- unsigned i, lockup;
- uint32_t *ptr;
- char fname[32];
-
- /* only dump the first cs to cause a lockup */
- if (!csc->crelocs) {
- /* can not determine if there was a lockup if no bo were use by
- * the cs and most likely in such case no lockup occurs
- */
- return;
- }
-
- memset(&args, 0, sizeof(args));
- args.handle = csc->relocs_bo[0].bo->handle;
- for (i = 0; i < RADEON_CS_DUMP_AFTER_MS_TIMEOUT; i++) {
- usleep(1);
- lockup = drmCommandWriteRead(csc->fd, DRM_RADEON_GEM_BUSY, &args, sizeof(args));
- if (!lockup) {
- break;
- }
- }
- if (!lockup || i < RADEON_CS_DUMP_AFTER_MS_TIMEOUT) {
- return;
- }
-
- ptr = radeon_bo_do_map(cs->trace_buf);
- fprintf(stderr, "timeout on cs lockup likely happen at cs 0x%08x dw 0x%08x\n", ptr[1], ptr[0]);
-
- if (csc->cs_trace_id != ptr[1]) {
- return;
- }
-
- /* ok we are most likely facing a lockup write the standalone replay file */
- snprintf(fname, sizeof(fname), "rlockup_0x%08x.c", csc->cs_trace_id);
- dump = fopen(fname, "w");
- if (dump == NULL) {
- return;
- }
- fprintf(dump, "/* To build this file you will need to copy radeon_ctx.h\n");
- fprintf(dump, " * in same directory. You can find radeon_ctx.h in mesa tree :\n");
- fprintf(dump, " * mesa/src/gallium/winsys/radeon/drm/radeon_ctx.h\n");
- fprintf(dump, " * Build with :\n");
- fprintf(dump, " * gcc -O0 -g `pkg-config --cflags --libs libdrm` %s -o rlockup_0x%08x \n", fname, csc->cs_trace_id);
- fprintf(dump, " */\n");
- fprintf(dump, " /* timeout on cs lockup likely happen at cs 0x%08x dw 0x%08x*/\n", ptr[1], ptr[0]);
- fprintf(dump, "#include <stdio.h>\n");
- fprintf(dump, "#include <stdint.h>\n");
- fprintf(dump, "#include \"radeon_ctx.h\"\n");
- fprintf(dump, "\n");
- fprintf(dump, "#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))\n");
- fprintf(dump, "\n");
-
- for (i = 0; i < csc->crelocs; i++) {
- unsigned j, ndw = (csc->relocs_bo[i].bo->base.size + 3) >> 2;
-
- ptr = radeon_bo_do_map(csc->relocs_bo[i].bo);
- if (ptr) {
- fprintf(dump, "static uint32_t bo_%04d_data[%d] = {\n ", i, ndw);
- for (j = 0; j < ndw; j++) {
- if (j && !(j % 8)) {
- uint32_t offset = (j - 8) << 2;
- fprintf(dump, " /* [0x%08x] va[0x%016"PRIx64"] */\n ", offset, offset + csc->relocs_bo[i].bo->va);
- }
- fprintf(dump, " 0x%08x,", ptr[j]);
- }
- fprintf(dump, "};\n\n");
- }
- }
-
- fprintf(dump, "static uint32_t bo_relocs[%d] = {\n", csc->crelocs * 4);
- for (i = 0; i < csc->crelocs; i++) {
- fprintf(dump, " 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
- 0, csc->relocs[i].read_domains, csc->relocs[i].write_domain, csc->relocs[i].flags);
- }
- fprintf(dump, "};\n\n");
-
- fprintf(dump, "/* cs %d dw */\n", csc->chunks[0].length_dw);
- fprintf(dump, "static uint32_t cs[] = {\n");
- ptr = csc->buf;
- for (i = 0; i < csc->chunks[0].length_dw; i++) {
- fprintf(dump, " 0x%08x,\n", ptr[i]);
- }
- fprintf(dump, "};\n\n");
-
- fprintf(dump, "static uint32_t cs_flags[2] = {\n");
- fprintf(dump, " 0x%08x,\n", csc->flags[0]);
- fprintf(dump, " 0x%08x,\n", csc->flags[1]);
- fprintf(dump, "};\n\n");
-
- fprintf(dump, "int main(int argc, char *argv[])\n");
- fprintf(dump, "{\n");
- fprintf(dump, " struct bo *bo[%d];\n", csc->crelocs);
- fprintf(dump, " struct ctx ctx;\n");
- fprintf(dump, "\n");
- fprintf(dump, " ctx_init(&ctx);\n");
- fprintf(dump, "\n");
-
- for (i = 0; i < csc->crelocs; i++) {
- unsigned ndw = (csc->relocs_bo[i].bo->base.size + 3) >> 2;
- uint32_t *ptr;
-
- ptr = radeon_bo_do_map(csc->relocs_bo[i].bo);
- if (ptr) {
- fprintf(dump, " bo[%d] = bo_new(&ctx, %d, bo_%04d_data, 0x%016"PRIx64", 0x%08x);\n",
- i, ndw, i, csc->relocs_bo[i].bo->va, csc->relocs_bo[i].bo->base.alignment);
- } else {
- fprintf(dump, " bo[%d] = bo_new(&ctx, %d, NULL, 0x%016"PRIx64", 0x%08x);\n",
- i, ndw, csc->relocs_bo[i].bo->va, csc->relocs_bo[i].bo->base.alignment);
- }
- }
- fprintf(dump, "\n");
- fprintf(dump, " ctx_cs(&ctx, cs, cs_flags, ARRAY_SIZE(cs), bo, bo_relocs, %d);\n", csc->crelocs);
- fprintf(dump, "\n");
- fprintf(dump, " fprintf(stderr, \"waiting for cs execution to end ....\\n\");\n");
- fprintf(dump, " bo_wait(&ctx, bo[0]);\n");
- fprintf(dump, "}\n");
- fclose(dump);
-}
projects / mesa.git / commitdiff