lib.fifo: make simulation read() and write() functions compat-only.

These functions were originally changed in 3ed51938, in an attempt
to make them take one cycle instead of two. However, this does not
actually work because of drawbacks of the simulator interface.

Avoid committing to any specific implementation for now, and instead
make them compat-only extensions.

diff --git a/nmigen/compat/genlib/fifo.py b/nmigen/compat/genlib/fifo.py
index 4e412d347425e515117bb83b3a44de735e28b147..c7d8c367d3816bb0935fadfb94ad8b57cc3cba58 100644 (file)
--- a/nmigen/compat/genlib/fifo.py
+++ b/nmigen/compat/genlib/fifo.py
@@ -1,4 +1,4 @@
-from ...tools import deprecated
+from ...tools import deprecated, extend
 from ...lib.fifo import FIFOInterface as NativeFIFOInterface, \
   SyncFIFO, SyncFIFOBuffered, AsyncFIFO, AsyncFIFOBuffered
 
@@ -14,3 +14,25 @@ class CompatFIFOInterface(NativeFIFOInterface):
 
 
 _FIFOInterface = CompatFIFOInterface
+
+
+@extend(NativeFIFOInterface)
+def read(self):
+    """Read method for simulation."""
+    assert (yield self.r_rdy)
+    value = (yield self.r_data)
+    yield self.r_en.eq(1)
+    yield
+    yield self.r_en.eq(0)
+    yield
+    return value
+
+@extend(NativeFIFOInterface)
+def write(self, data):
+    """Write method for simulation."""
+    assert (yield self.w_rdy)
+    yield self.w_data.eq(data)
+    yield self.w_en.eq(1)
+    yield
+    yield self.w_en.eq(0)
+    yield

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index 638a77e98902675984c9c51c5f85ba62e73cc89d..9be6003fe1291b0f87ebe94d4bda20678b4cc488 100644 (file)
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -73,23 +73,6 @@ class FIFOInterface:
         self.r_rdy  = Signal() # not empty
         self.r_en   = Signal()
 
-    def read(self):
-        """Read method for simulation."""
-        assert (yield self.r_rdy)
-        yield self.r_en.eq(1)
-        yield
-        value = (yield self.r_data)
-        yield self.r_en.eq(0)
-        return value
-
-    def write(self, data):
-        """Write method for simulation."""
-        assert (yield self.w_rdy)
-        yield self.w_data.eq(data)
-        yield self.w_en.eq(1)
-        yield
-        yield self.w_en.eq(0)
-
     # TODO(nmigen-0.2): move this to nmigen.compat and make it a deprecated extension
     @property
     @deprecated("instead of `fifo.din`, use `fifo.w_data`")

diff --git a/nmigen/test/test_lib_fifo.py b/nmigen/test/test_lib_fifo.py
index 9a8c9c182a9f0b3eb350224cdd48279f6236d8b5..93ad95b1cfa65c3bd1fd0817546e5fc11887ee08 100644 (file)
--- a/nmigen/test/test_lib_fifo.py
+++ b/nmigen/test/test_lib_fifo.py
@@ -5,42 +5,6 @@ from ..back.pysim import *
 from ..lib.fifo import *
 
 
-class FIFOSmokeTestCase(FHDLTestCase):
-    def assertSyncFIFOWorks(self, fifo, xfrm=lambda x: x):
-        with Simulator(xfrm(Fragment.get(fifo, None)), vcd_file=open("test.vcd", "w")) as sim:
-            sim.add_clock(1e-6)
-            def process():
-                yield from fifo.write(1)
-                yield from fifo.write(2)
-                while not (yield fifo.r_rdy):
-                    yield
-                if not fifo.fwft:
-                    yield fifo.r_en.eq(1)
-                yield
-                self.assertEqual((yield from fifo.read()), 1)
-                self.assertEqual((yield from fifo.read()), 2)
-            sim.add_sync_process(process)
-            sim.run()
-
-    def assertAsyncFIFOWorks(self, fifo):
-        self.assertSyncFIFOWorks(fifo, xfrm=DomainRenamer({"read": "sync", "write": "sync"}))
-
-    def test_sync_fwft(self):
-        self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=True))
-
-    def test_sync_not_fwft(self):
-        self.assertSyncFIFOWorks(SyncFIFO(width=8, depth=4, fwft=False))
-
-    def test_sync_buffered(self):
-        self.assertSyncFIFOWorks(SyncFIFOBuffered(width=8, depth=4))
-
-    def test_async(self):
-        self.assertAsyncFIFOWorks(AsyncFIFO(width=8, depth=4))
-
-    def test_async_buffered(self):
-        self.assertAsyncFIFOWorks(AsyncFIFOBuffered(width=8, depth=3))
-
-
 class FIFOModel(Elaboratable, FIFOInterface):
     """
     Non-synthesizable first-in first-out queue, implemented naively as a chain of registers.