litex/build/io: also import CRG (since using DifferentialInput).

diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index 5ac6b2306f64b1f8685c9378bc1c026e2719e500..cb42704895318c54c06c5a61d54e2267392ffa32 100755 (executable)
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -20,9 +20,6 @@ from litedram.phy import s7ddrphy
 
 from liteeth.phy.rmii import LiteEthPHYRMII
 
-from litespi import LiteSPI
-from litespi.phy.generic import LiteSPIPHY
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -78,6 +75,8 @@ class BaseSoC(SoCCore):
 
         # SPI XIP ----------------------------------------------------------------------------------
         if with_spi_xip:
+            from litespi import LiteSPI
+            from litespi.phy.generic import LiteSPIPHY
             spi_xip_size = 1024*1024*8
             self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
             self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index b7befc894c53624e67270bf00c7faec2dbfabeef..b208544fb52a35885389d2ccb19b3990e8802894 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -8,7 +8,8 @@ import argparse
 import importlib
 
 from migen import *
-from migen.genlib.io import CRG
+
+from litex.build.io import CRG
 
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *

diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index 65d70665882ef46b366ea34ba2bee128a2b4d5f6..d540cc38a4e533c9d763bc6cf5a9fd25a0b6f643 100644 (file)
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -7,10 +7,10 @@ import os
 
 from migen.fhdl.structure import Signal
 from migen.genlib.record import Record
-from migen.genlib.io import CRG
 
 from litex.gen.fhdl import verilog
 
+from litex.build.io import CRG
 from litex.build import tools
 
 

diff --git a/litex/build/io.py b/litex/build/io.py
index 690477a9b1cf18e9f7a8d21ce75e56c193379e37..a052973ca65e21c0fa3911569786cff5a66086ad 100644 (file)
--- a/litex/build/io.py
+++ b/litex/build/io.py
@@ -1,4 +1,5 @@
 # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
 # License: BSD
 
 from migen import *
@@ -39,7 +40,6 @@ class DifferentialOutput(Special):
     def lower(dr):
         raise NotImplementedError("Attempted to use a Differential Output, but platform does not support them")
 
-
 # SDR Input/Output ---------------------------------------------------------------------------------
 
 class InferedSDRIO(Module):
@@ -111,3 +111,24 @@ class DDROutput(Special):
     @staticmethod
     def lower(dr):
         raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
+
+# Clock Reset Generator ----------------------------------------------------------------------------
+
+class CRG(Module):
+    def __init__(self, clk, rst=0):
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_por = ClockDomain(reset_less=True)
+
+        if hasattr(clk, "p"):
+            clk_se = Signal()
+            self.specials += DifferentialInput(clk.p, clk.n, clk_se)
+            clk = clk_se
+
+        # Power on Reset (vendor agnostic)
+        int_rst = Signal(reset=1)
+        self.sync.por += int_rst.eq(rst)
+        self.comb += [
+            self.cd_sys.clk.eq(clk),
+            self.cd_por.clk.eq(clk),
+            self.cd_sys.rst.eq(int_rst)
+        ]