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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 92173807a1327d542be4028230b96542926f0e1d..ec20d02f91747573f89508fd3a0471e8fa566b7c 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -215,7 +215,7 @@ them to a risky niche market?
 
 # How do you turn a Scalar ISA into a Vector one?
 
-The most obvious question before that is: why would you want to?
+The most obvious question before that is: why on earth would you want to?
 As explained in the "SIMD Considered Harmful" article, Cray-style
 Vector ISAs break the link between data element batches and the
 underlying architectural back-end parallel processing capability.
@@ -245,7 +245,9 @@ Vector instructions in RISC-V as there are in the RV64GC Scalar base.
 The question then becomes: with all the duplication of arithmetic
 operations just to make the registers scalar or vector, why not
 leverage the *existing* Scalar ISA with some sort of "context"
-or prefix that augments its behaviour?
+or prefix that augments its behaviour?  Then, the Instruction Decode
+phase is greatly simplified, reducing design complexity and leaving
+plenty of headroom for further expansion.
 
 Remarkably this is not a new idea.  Intel's x86 `REP` instruction
 gives the base concept, but in 1994 it was Peter Hsu, the designer