ac_dump_module(llvm_module);
memset(binary, 0, sizeof(*binary));
+
+ if (options->record_llvm_ir) {
+ char *llvm_ir = LLVMPrintModuleToString(llvm_module);
+ binary->llvm_ir_string = strdup(llvm_ir);
+ LLVMDisposeMessage(llvm_ir);
+ }
+
int v = ac_llvm_compile(llvm_module, binary, tm);
if (v) {
fprintf(stderr, "compile failed\n");
options->dump_shader = radv_can_dump_shader(device, module);
options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
+ options->record_llvm_ir = device->keep_shader_info;
if (options->supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
if (device->keep_shader_info) {
variant->disasm_string = binary.disasm_string;
+ variant->llvm_ir_string = binary.llvm_ir_string;
if (!gs_copy_shader && !module->nir) {
variant->nir = *shaders;
variant->spirv = (uint32_t *)module->data;
ralloc_free(variant->nir);
free(variant->disasm_string);
+ free(variant->llvm_ir_string);
free(variant);
}
bool clamp_shadow_reference;
bool dump_shader;
bool dump_preoptir;
+ bool record_llvm_ir;
enum radeon_family family;
enum chip_class chip_class;
};
uint32_t spirv_size;
struct nir_shader *nir;
char *disasm_string;
+ char *llvm_ir_string;
struct list_head slab_list;
};