rs6000: wj -> wi+p8v

Also deletes VS_64dm, it's unused.

	* config/rs6000/constraints.md (define_register_constraint "wj"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wj.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wj" constraint by "wi" with "p8v".
	(VS_64dm): Delete.
	* config/rs6000/vsx.md: Ditto.
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271484

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce52649f31fe32cfe7541bd085c9bed3de0d639b..2568eae098282878d96985d622fe5bbee0ef6fa8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2019-05-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/constraints.md (define_register_constraint "wj"):
+       Delete.
+       * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+       RS6000_CONSTRAINT_wj.
+       * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+       (rs6000_init_hard_regno_mode_ok): Adjust.
+       * config/rs6000/rs6000.md: Replace "wj" constraint by "wi" with "p8v".
+       (VS_64dm): Delete.
+       * config/rs6000/vsx.md: Ditto.
+       * doc/md.texi (Machine Constraints): Adjust.
+
 2019-05-21  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/constraints.md (define_register_constraint "wh"):

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index c9f168f0b1d4d990f5dcba582d85db1810ddae08..9f315e462c31a4092791994e3ecaa25244cdb1e0 100644 (file)
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -74,9 +74,6 @@
 (define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
   "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
 
-(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
-  "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
-
 (define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
   "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1a4cb76a8a104a91c64e523119358e3500de3f90..e88a829860a7ee5224fe8a6fa8a44bf37e220c6d 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void)
           "wf reg_class = %s\n"
           "wg reg_class = %s\n"
           "wi reg_class = %s\n"
-          "wj reg_class = %s\n"
           "wk reg_class = %s\n"
           "wl reg_class = %s\n"
           "wm reg_class = %s\n"
@@ -2537,7 +2536,6 @@ rs6000_debug_reg_global (void)
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
-          reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
@@ -3162,7 +3160,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
        wf - Preferred register class for V4SFmode.
        wg - Float register for power6x move insns.
        wi - FP or VSX register to hold 64-bit integers for VSX insns.
-       wj - FP or VSX register to hold 64-bit integers for direct moves.
        wk - FP or VSX register to hold 64-bit doubles for direct moves.
        wl - Float register if we can do 32-bit signed int loads.
        wm - VSX register for ISA 2.07 direct move operations.
@@ -3205,8 +3202,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
   if (TARGET_DIRECT_MOVE)
     {
-      rs6000_constraints[RS6000_CONSTRAINT_wj]                 /* DImode  */
-       = rs6000_constraints[RS6000_CONSTRAINT_wi];
       rs6000_constraints[RS6000_CONSTRAINT_wk]                 /* DFmode  */
        = rs6000_constraints[RS6000_CONSTRAINT_ws];
       rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ca30639ff5c58f4b6f5016df040dd8885abada48..218ed10dea3a52e3631c87bd32983f310fd130c3 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wf,                /* VSX register for V4SF */
   RS6000_CONSTRAINT_wg,                /* FPR register for -mmfpgpr */
   RS6000_CONSTRAINT_wi,                /* FPR/VSX register to hold DImode */
-  RS6000_CONSTRAINT_wj,                /* FPR/VSX register for DImode direct moves. */
   RS6000_CONSTRAINT_wk,                /* FPR/VSX register for DFmode direct moves. */
   RS6000_CONSTRAINT_wl,                /* FPR register for LFIWAX */
   RS6000_CONSTRAINT_wm,                /* VSX register for direct move */

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 398398ca8cff775df3a60c515cc7fde709c1e77a..9a986a147f403f2a41a5900c34f4595e4c61e92f 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -834,7 +834,7 @@
 
 
 (define_insn "zero_extendsi<mode>2"
-  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wj,r,wa")
+  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wi,r,wa")
        (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
   ""
   "@
@@ -846,7 +846,7 @@
    mfvsrwz %0,%x1
    xxextractuw %x0,%x1,4"
   [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")
-   (set_attr "isa" "*,*,*,p8v,*,p8v,p9v")])
+   (set_attr "isa" "*,*,*,p8v,p8v,p8v,p9v")])
 
 (define_insn_and_split "*zero_extendsi<mode>2_dot"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
@@ -1019,7 +1019,7 @@
 
 (define_insn "extendsi<mode>2"
   [(set (match_operand:EXTSI 0 "gpc_reg_operand"
-                    "=r, r,   wl,    wa,    wj,    v,      v,     wr")
+                    "=r, r,   wl,    wa,    wi,    v,      v,     wr")
        (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
                     "YZ, r,   Z,     Z,     r,     v,      v,     ?wa")))]
   ""
@@ -1035,7 +1035,7 @@
   [(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
    (set_attr "sign_extend" "yes")
    (set_attr "length" "4,4,4,4,4,4,8,8")
-   (set_attr "isa" "*,*,*,p8v,*,p9v,p8v,p8v")])
+   (set_attr "isa" "*,*,*,p8v,p8v,p9v,p8v,p8v")])
 
 (define_split
   [(set (match_operand:EXTSI 0 "int_reg_operand")
@@ -5233,7 +5233,7 @@
 ; We don't define lfiwax/lfiwzx with the normal definition, because we
 ; don't want to support putting SImode in FPR registers.
 (define_insn "lfiwax"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,v")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,v")
        (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,v")]
                   UNSPEC_LFIWAX))]
   "TARGET_HARD_FLOAT && TARGET_LFIWAX"
@@ -5243,7 +5243,7 @@
    mtvsrwa %x0,%1
    vextsw2d %0,%1"
   [(set_attr "type" "fpload,fpload,mffgpr,vecexts")
-   (set_attr "isa" "*,*,*,p9v")])
+   (set_attr "isa" "*,p8v,p8v,p9v")])
 
 ; This split must be run before register allocation because it allocates the
 ; memory slot that is needed to move values to/from the FPR.  We don't allocate
@@ -5315,7 +5315,7 @@
    (set_attr "type" "fpload")])
 
 (define_insn "lfiwzx"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wa")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,wa")
        (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")]
                   UNSPEC_LFIWZX))]
   "TARGET_HARD_FLOAT && TARGET_LFIWZX"
@@ -5325,7 +5325,7 @@
    mtvsrwz %x0,%1
    xxextractuw %x0,%x1,4"
   [(set_attr "type" "fpload,fpload,mftgpr,vecexts")
-   (set_attr "isa" "*,*,*,p9v")])
+   (set_attr "isa" "*,p8v,p8v,p9v")])
 
 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
@@ -8831,13 +8831,13 @@
                 m,         ^d,        ^d,        wY,        Z,          $v,
                 $wv,       ^wi,       wa,        wa,        wv,         wi,
                 wi,        wv,        wv,        r,         *h,         *h,
-                ?r,        ?wg,       ?r,        ?wj")
+                ?r,        ?wg,       ?r,        ?wi")
        (match_operand:DI 1 "input_operand"
                "r,         YZ,        r,         I,         L,          nF,
                 ^d,        m,         ^d,        ^v,        $wv,        wY,
                 Z,         ^wi,       Oj,        wM,        OjwM,       Oj,
                 wM,        wS,        wB,        *h,        r,          0,
-                wg,        r,         wj,        r"))]
+                wg,        r,         wi,        r"))]
   "TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], DImode)
        || gpc_reg_operand (operands[1], DImode))"
@@ -8888,7 +8888,7 @@
                 *,         *,         *,         p9v,       *,          p9v,
                 *,         *,         p9v,       p9v,       *,          *,
                 *,         *,         *,         *,         *,          *,
-                *,         *,         *,         *")])
+                *,         *,         p8v,       p8v")])
 
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ae757f183d023f9569a888c3da11606fb75242fc..ff4ceb6268fe86556393eb66f6bf8343933acf62 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -275,11 +275,6 @@
                             (V2DF      "V4DF")
                             (V1TI      "V2TI")])
 
-;; Map register class for 64-bit element in 128-bit vector for direct moves
-;; to/from gprs
-(define_mode_attr VS_64dm [(V2DF       "wk")
-                          (V2DI        "wj")])
-
 ;; Map register class for 64-bit element in 128-bit vector for normal register
 ;; to register moves
 (define_mode_attr VS_64reg [(V2DF      "ws")
@@ -4158,12 +4153,13 @@
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we")
        (vec_duplicate:V4SI
         (truncate:SI
-         (match_operand:DI 1 "gpc_reg_operand" "wj,r"))))]
+         (match_operand:DI 1 "gpc_reg_operand" "wi,r"))))]
   "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
   "@
    xxspltw %x0,%x1,1
    mtvsrws %x0,%1"
-  [(set_attr "type" "vecperm")])
+  [(set_attr "type" "vecperm")
+   (set_attr "isa" "p8v,*")])
 
 ;; V4SF splat (ISA 3.0)
 (define_insn_and_split "vsx_splat_v4sf"

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index daf0195fe3bf7ad41f70f1f200676cab2cbb203f..55de2f1b37ce73ea996ca50a4ee63dcd2b0ccd93 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
 
 When using any of the register constraints (@code{wa}, @code{wd},
-@code{wf}, @code{wg}, @code{wi}, @code{wj}, @code{wk},
+@code{wf}, @code{wg}, @code{wi}, @code{wk},
 @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
 @code{wt}, @code{wv}, or @code{ww})
 that take VSX registers, you must use @code{%x<n>} in the template so
@@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
 @item wi
 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
 
-@item wj
-FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
-
 @item wk
 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.